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MICROCHIP MCP2517FDT-H/SL product image
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MICROCHIP MCP2517FDT-H/SLRoHS

Manufacturer
MICROCHIP
MPN
MCP2517FDT-H/SL
LCSC Part #
C512185
Packaging
SOIC-14
Customer #
Key Attributes
External CAN FD Controller with SPI Interface
Datasheetpdf iconMICROCHIP MCP2517FDT-H/SL
In-Stock: 230
230 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 3.8665$ 3.87
10+$ 3.4079$ 34.08
30+$ 3.1211$ 93.63
100+$ 2.8261$ 282.61
500+$ 2.6933$ 1346.65
1,000+$ 2.6365$ 2636.50
Standard Packaging2600/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/Interface Controllers
ManufacturerMICROCHIP
PackagingSOIC-14
FeaturesAuto retransmission control;Monitor mode;Low-power mode
Operating Temperature-40℃~+150℃
Voltage - Supply2.7V~5.5V
ProtocolSPI
Data Rate8Mbps
TypeCAN FD Controller
Supply Current20mA
Quiescent Supply Current10uA
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2600
Sales UnitPiece

Introduction

AI Translation

The MCP2517FD is a cost-effective and small-footprint CAN FD controller that can be easily added to a microcontroller with an available SPI interface. Therefore, a CAN FD channel can be easily added to a microcontroller that is either lacking a CAN FD peripheral, or that doesn’t have enough CAN FD channels. The MCP2517FD supports both, CAN frames in the Classical format (CAN2.0B) and CAN Flexible Data Rate (CAN FD) format, as specified in ISO 11898 - 1:2015.

Features

AI Translation
  • External CAN FD Controller with SPI Interface
  • Arbitration Bit Rate up to 1 Mbps
  • Data Bit Rate up to 8 Mbps
  • CAN FD Controller modes - Mixed CAN 2.0B and CAN FD mode - CAN 2.0B mode
  • Conforms to ISO 11898-1:2015
  • 31 FIFOs, configurable as transmit or receive FIFOs
  • One Transmit Queue (TXQ)
  • Transmit Event FIFO (TEF) with 32 bit time stamp
  • Message transmission prioritization: - Based on priority bit field, and/or - Message with lowest ID gets transmitted first using the Transmit Queue (TXQ)
  • Programmable automatic retransmission attempts: unlimited, 3 attempts or disabled
  • 32 Flexible Filter and Mask Objects
  • Each object can be configured to filter either: - Standard ID + first 18 data bits, or - Extended ID
  • 32-bit Time Stamp
  • VDD: 2.7 to 5.5V
  • Active current: max. 20 mA at 5.5 V, 40 MHz CAN clock
  • Sleep current: 10 μA, typical
  • Message objects are located in RAM: 2 KB
  • Up to 3 configurable interrupt pins
  • Bus Health Diagnostics and Error counters
  • Transceiver standby control
  • Start of frame pin for indicating the beginning of messages on the bus
  • Temperature ranges: - High (H): -40°C to +150°C
  • 40, 20 or 4 MHz crystal, or ceramic resonator; or external clock input
  • Clock output with prescaler
  • Up to 20 MHz SPI clock speed
  • Supports SPI modes 0,0 and 1,1
  • Registers and bit fields are arranged in a way to enable efficient access via SPI
  • SPI commands with CRC to detect noise on SPI interface
  • Error Correction Code (ECC) protected RAM
  • GPIO pins: INT0 and INT1 can be configured as general purpose I/O
  • Open drain outputs: TXCAN, INT, INT0, and INT1 pins can be configured as push/pull or open drain outputs