ISSI IS25LP256E-JLLE

The IS25LP256E and IS25WP256E Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O. The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 166MHz allow for equivalent clock rates of up to 664MHz (166MHz x 4) which equates to 83Mbytes/s of data throughput. The IS25xE series of Flash adds support for DTR (Double Transfer Rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation. Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory. QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64K/256Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allowes for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention.

• Industry Standard Serial Interface
• IS25LP256E: 256Mbit/32Mbyte - IS25WP256E: 256Mbit/32Mbyte
• 3 or 4 Byte Addressing Mode
• Supports Standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI
• Software & Hardware Reset
• Supports Serial Flash Discoverable Parameters (SFDP)
• High Performance Serial Flash (SPI)
• 50MHz Normal Read
• Up to166Mhz Fast Read (4)
• Up to 80MHz DTR (Dual Transfer Rate)
• Equivalent Throughput of 664 Mb/s
• Selectable Dummy Cycles
• Configurable Drive Strength
• Supports SPI Modes 0 and 3
• More than 100,000 Erase/Program Cycles
• More than 20-year Data Retention
• Flexible & Efficient Memory Architecture
• Chip Erase with Uniform Sector/Block Erase (4/32/64KB or 4/32/256 KB)
• Program 1 to 256 or 512 Byte per Page
• Program/Erase Suspend & Resume
• Efficient Read and Program modes
• Low Instruction Overhead Operations
• Continuous Read 8/16/32/64 Byte Burst Wrap
• Selectable Burst Length
• QPI for Reduced Instruction Overhead
• AutoBoot Operation
• Data Learning Pattern for training in DTR operation
• Low Power with Wide Temp. Ranges
• Single Voltage Supply IS25LP: 2.30V to 3.60V IS25WP: 1.70V to 1.95V
• 7 mA Active Read Current
• 10 μA Standby Current
• 1 μA Deep Power Down
• Temp Grades: Extended: -40℃ to +105℃ Auto Grade (A3): -40℃ to +125℃
• Advanced Security Protection
• Software and Hardware Write Protection
• Advanced Sector/Block Protection
• Top/Bottom Block Protection
• Power Supply Lock Protection
• 4x256 Byte Dedicated Security Area with OTP User-lockable Bits
• 128 bit Unique ID for Each Device (Call Factory)
• Industry Standard Pin-out & Packages
• M = 16-pin SOIC 300mil
• L = 8-contact WSON 8x6mm
• J = 8-contact WSON 8x6mm
• G = 24-ball TFBGA 6x8mm (4x6 ball array)
• H = 24-ball TFBGA 6x8mm (5x5 ball array)
• KGD (Call Factory)