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TI SN74LVC2G86DCUR
| Manufacturer | |
| MPN | SN74LVC2G86DCUR |
| LCSC Part # | C507252 |
| Packaging | VSSOP-8 |
| Customer # | |
| Key Attributes | Dual 2-Input Exclusive-OR Gate |
| Datasheet |  TI SN74LVC2G86DCUR |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | TI | |
| Packaging | VSSOP-8 | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | 450mV;300mV;400mV;550mV | |
| Propagation Delay | 4.7ns@3.3V | |
| Features | Live insertion protection;Local shutdown mode;Rear drive protection | |
| Input Logic Level - Low | 700mV;800mV | |
| Input Logic Level - High | 1.7V;2V | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | 1.2V;1.9V;2.4V;2.3V;3.8V | |
| Quiescent Current(Iq) | 10uA | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
Available in the NanoFree™ Package Supports 5-V Vcc Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.7 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3V, TA = 25℃ Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3V, TA = 25℃ Ioff Supports Live Insertion, Partial-Power Down Mode and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-VCC operation.
The SN74LVC2G86 performs the Boolean function Y = A⊕B or Y = A(overline)B + A(overline)B(overline) in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.2958 | $ 1.48 |
| 50+ | $ 0.2314 | $ 11.57 |
| 150+ | $ 0.2038 | $ 30.57 |
| 500+ | $ 0.1694 | $ 84.70 |
| 3,000+ | $ 0.154 | $ 462.00 |
| 6,000+ | $ 0.1448 | $ 868.80 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | TI | |
| Packaging | VSSOP-8 | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | 450mV;300mV;400mV;550mV | |
| Propagation Delay | 4.7ns@3.3V | |
| Features | Live insertion protection;Local shutdown mode;Rear drive protection | |
| Input Logic Level - Low | 700mV;800mV | |
| Input Logic Level - High | 1.7V;2V | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | 1.2V;1.9V;2.4V;2.3V;3.8V | |
| Quiescent Current(Iq) | 10uA | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
Available in the NanoFree™ Package Supports 5-V Vcc Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.7 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3V, TA = 25℃ Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3V, TA = 25℃ Ioff Supports Live Insertion, Partial-Power Down Mode and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-VCC operation.
The SN74LVC2G86 performs the Boolean function Y = A⊕B or Y = A(overline)B + A(overline)B(overline) in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |