MXIC MX25U51245GMI00
| Manufacturer | |
| MPN | MX25U51245GMI00 |
| LCSC Part # | C505512 |
| Packaging | SOP-16-300mil |
| Customer # | |
| Key Attributes | CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | MXIC | |
| Packaging | SOP-16-300mil | |
| Memory Size | 512Mbit | |
| Voltage - Supply | 1.65V~2V | |
| Operating temperature | -40℃~+85℃ | |
| Program / Erase Cycles | 100,000 cycles | |
| Clock Frequency | 166MHz | |
| Data Retention - TDR (Year) | 20 Years | |
| Page Programming Time (Tpp) | 150us | |
| Interface | SPI |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 44 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
1.8V 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
Features
AI Translation
- GENERAL
- Supports Serial Peripheral Interface -- Mode 0 and Mode 3
- Single Power Supply Operation - 1.65 to 2.0 volt for read, erase, and program operations
- 512Mb: 536,870,912 x 1 bit structure or 268,435,456×2 bits (two I/O mode) structure or 134,217,728×4 bits (four I/O mode) structure
- Protocol Support - Single I/O, Dual I/O and Quad I/O
- Latch-up protected to 100mA from -1V to Vcc +1V
- Fast read for SPI mode - Support fast clock frequency up to 166MHz - Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions - Support DTR (Double Transfer Rate) Mode - Configurable dummy cycle number for fast read operation
- Quad Peripheral Interface (QPI) available
- Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually
- Programming : - 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance
- Typical 100,000 erase/program cycles
- 20 years data retention
- SOFTWARE FEATURES
- Input Data Format - 1-byte Command code
- Advanced Security Features - Block lock protection The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase instructions - Advanced sector protection function
- Additional 8K bit security OTP - Features unique identifier - Factory locked identifiable, and customer lockable
- Command Reset
- Program/Erase Suspend and Resume operation Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID
- Support Serial Flash Discoverable Parameters (SFDP) mode
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 10.6716 | $ 10.67 |
| 10+ | $ 9.8609 | $ 98.61 |
| 30+ | $ 9.3678 | $ 281.03 |
| 100+ | $ 8.9529 | $ 895.29 |
Standard Packaging44/Full Tube | ||
Better price for more quantity?
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | MXIC | |
| Packaging | SOP-16-300mil | |
| Memory Size | 512Mbit | |
| Voltage - Supply | 1.65V~2V | |
| Operating temperature | -40℃~+85℃ | |
| Program / Erase Cycles | 100,000 cycles | |
| Clock Frequency | 166MHz | |
| Data Retention - TDR (Year) | 20 Years | |
| Page Programming Time (Tpp) | 150us | |
| Interface | SPI |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 44 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
1.8V 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
Features
AI Translation
- GENERAL
- Supports Serial Peripheral Interface -- Mode 0 and Mode 3
- Single Power Supply Operation - 1.65 to 2.0 volt for read, erase, and program operations
- 512Mb: 536,870,912 x 1 bit structure or 268,435,456×2 bits (two I/O mode) structure or 134,217,728×4 bits (four I/O mode) structure
- Protocol Support - Single I/O, Dual I/O and Quad I/O
- Latch-up protected to 100mA from -1V to Vcc +1V
- Fast read for SPI mode - Support fast clock frequency up to 166MHz - Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions - Support DTR (Double Transfer Rate) Mode - Configurable dummy cycle number for fast read operation
- Quad Peripheral Interface (QPI) available
- Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually
- Programming : - 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance
- Typical 100,000 erase/program cycles
- 20 years data retention
- SOFTWARE FEATURES
- Input Data Format - 1-byte Command code
- Advanced Security Features - Block lock protection The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase instructions - Advanced sector protection function
- Additional 8K bit security OTP - Features unique identifier - Factory locked identifiable, and customer lockable
- Command Reset
- Program/Erase Suspend and Resume operation Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID
- Support Serial Flash Discoverable Parameters (SFDP) mode
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991B1A |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991B1A |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |



