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TI CD4001BPWRRoHS

Manufacturer
TI
MPN
CD4001BPWR
LCSC Part #
C496116
Packaging
TSSOP-14
Customer #
Key Attributes
CMOS NOR Gates
Datasheetpdf iconTI CD4001BPWR
In-Stock: 2,898
2,898 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.4132$ 0.41
10+$ 0.3257$ 3.26
30+$ 0.282$ 8.46
100+$ 0.2431$ 24.31
500+$ 0.2318$ 115.90
1,000+$ 0.2253$ 225.30
Standard Packaging2000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerTI
PackagingTSSOP-14
Features-
Input Logic Level - High3.5V~11V
Input Logic Level - Low1.5V~4V
Operating Temperature-55℃~+125℃
Logic Family4000B Series
Output Logic Level - High4.95V;9.95V;14.95V
Quiescent Current(Iq)1uA
Voltage - Supply3V~18V
Current - Output High(IOH)3.4mA
Number of Channels4;2
Output Logic Level - Low50mV
Propagation Delay90ns@15V,50pF
Current - Output Low(IOL)3.4mA
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4001B, CD4002B, and CD4025B types are supplied in 14 - lead hermetic dual - in - line ceramic packages (F3A suffix), 14 - lead dual - in - line plastic packages (E suffix), 14 - lead small - outline packages (M, MT, M96, and NSR suffixes), and 14 - lead thin shrink small - outline packages (PW and PWR suffixes).

Features

AI Translation
  • Propagation delay time = 60 ns (typ.) at cL = 50 pF, VDD = 90 V
  • Buffered inputs and outputs
  • Standardized symmetrical output characteristics, 700% tested for maximum quiescent current at 20 V
  • 5 - V, 10 - V, and 15 - V parametric ratings
  • Maximum input current of 1 μA at 18 V over full package - temperature range; 100 nA at VDD and 25℃
  • Noise margin (over full package temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V