Zbit Semi ZB25VQ16ATIG

The ZB25VQ16 of non-volatile flash memory device supports the standard Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (quad I/O) serial protocols. This multiple width interface is called SPI Multi-I/O or MIO. The SPI protocols use only 4 to 6 signals: Chip Select (CS#) Serial Clock (CLK) Serial Data

• IO0 (DI)
• IO1 (DO)
• IO2 (WP#)
• IO3 (HOLD# / RESET#) The ZB25VQ16 support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-clocks instruction cycle Quad Peripheral Interface : Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (WP#), and I/O3 (HOLD# / RESET#). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and SFD

• Low power supply operation - Single 2.3V-3.6V supply
• 16M bit Serial Flash - 16 M-bit/2048K-byte/8,192 pages 256 bytes per programmable page Uniform 4K-byte Sectors, 32K/64K-byte Blocks
• Standard SPI: CLK, CS#, DI, DO, WP#, HOLD# / RESET#
• Dual SPI: CLK, CS#, DI, DO, WP#, HOLD# / RESET#
• Quad SPI: CLK, CS#, IO0, IO1, IO2, IO3
• Software & Hardware Reset
• Auto-increment Read capability
• Temperature Ranges: Industrial (-40℃ to +85℃) - Extended (-20℃ to +85℃)
• Low power consumption - 9 mA typical active current - 3 uA typical power down current - Continuous Read with 8/16/32/64-Byte Wrap As few as 8 clocks to address memory - Quad Peripheral Interface reduces instruction overhead
• Flexible Architecture with 4KB sectors Sector Erase (4K-bytes) Block Erase (32K/64K-bytes) Page Program up to 256 bytes More than 100K erase/program cycles - More than 20-year data retention
• Advanced Security Feature: Software and Hardware Write-Protect, Power Supply Lock-Down and OTP protection, Top/Bottom, Complement array protection, 64-Bit Unique ID for each device, Discoverable parameters(SFDP) register, 3X256-Bytes Security Registers with OTP locks, Volatile & Non-volatile Status Register Bits
• High performance program/erase speed Page program time: 600us typical Sector erase time: 40ms typical Block erase time: 200ms typical Chip erase time: 8s typical
• Package Options: SOP8 - 150mil/208mil TFBGA24 TSSOP8 - 173mil DFN8 (430.55mm) All Pb-free packages are RoHS compliant