LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
EnergyMath EM74LVC1G08GS product image
  • EM74LVC1G08GS thumbnail 1
  • EM74LVC1G08GS thumbnail 2
  • EM74LVC1G08GS thumbnail 3
  • Pinout
  • Footprint
Images for reference only

EnergyMath EM74LVC1G08GSRoHS

Manufacturer
EnergyMathAsian Brands
MPN
EM74LVC1G08GS
LCSC Part #
C49188146
Packaging
DFN-6L(1x1)
Customer #
Key Attributes
Single 2-input AND gate
Datasheetpdf iconEnergyMath EM74LVC1G08GS
In-Stock: 3,000
3,000 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
5+$ 0.0976$ 0.49
50+$ 0.0776$ 3.88
150+$ 0.0677$ 10.16
500+$ 0.0602$ 30.10
3,000+$ 0.0542$ 162.60
6,000+$ 0.0512$ 307.20
Standard Packaging3000/Full Reel
Better price for more quantity?
$

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerEnergyMath
PackagingDFN-6L(1x1)
Input Logic Level - High-
Input Logic Level - Low-
FeaturesLocal shutdown mode;Overvoltage-tolerant input
Operating Temperature-40℃~+125℃
Logic Family74LVC
Output Logic Level - High-
Quiescent Current(Iq)4uA
Voltage - Supply1.65V~5.5V
Current - Output High(IOH)24mA
Number of Channels1;2
Output Logic Level - Low-
Propagation Delay3.8ns@5.5V,50pF
Current - Output Low(IOL)24mA

Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging3000
Sales UnitPiece

Introduction

AI Translation

The EM74LVC1G08 is a single 2-input AND gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V applications. All inputs incorporate Schmitt-trigger action, making the circuit tolerant of slower input rise and fall times. The device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the outputs, preventing damaging backflow current when the device is powered down.

Features

AI Translation
  • Wide supply voltage range: 1.65 V ~ 5.5 V
  • High noise immunity
  • ±24 mA output drive capability (VCC = 3.0V)
  • CMOS low power consumption
  • Direct TTL-level interface compatible
  • Over-voltage tolerant inputs up to 5.5 V
  • IOFF circuitry supports partial power-down mode operation
  • Latch-up performance exceeds 100 mA
  • JEDEC standard compliant: JESD8-7 (1.65 V ~ 1.95 V), JESD8-5 (2.3 V ~ 2.7 V), JESD8C (2.7 V ~ 3.6 V), JESD36 (4.5 V ~ 5.5 V)
  • ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V; MM JESD22-A115C Class C exceeds 550 V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
  • Multiple package options