EnergyMath EM74LVC2G14GW
| Manufacturer | EnergyMathAsian Brands |
| MPN | EM74LVC2G14GW |
| LCSC Part # | C49188097 |
| Packaging | SOT-363 |
| Customer # | |
| Key Attributes | Dual inverting Schmitt trigger with 5V tolerant input |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | EnergyMath | |
| Packaging | SOT-363 | |
| Logic Family | 74LVC | |
| Input Type | Schmitt trigger | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | - | |
| Propagation Delay | 2.9ns@4.5V,50pF | |
| Features | Power shutdown protection;Noise suppression function | |
| Input Logic Level - Low | - | |
| Input Logic Level - High | - | |
| Operating Temperature | -40℃~+125℃ | |
| Number of Circuits | 2 | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 4uA | |
| Number of Channels | - | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 10 |
| Multiple | 10 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The EM74LVC2G14 is a dual inverter with Schmitt-trigger inputs. Its inputs can be driven by 3.3 V or 5 V devices. This feature allows the device to be used as a level translator in mixed 3.3 V and 5 V environments. The device is fully specified for partial-power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging backflow current when the device is powered down.
Features
- Wide supply voltage range: 1.65 V to 5.5 V
- Input overvoltage tolerance up to 5.5 V
- High noise immunity
- ±24 mA output drive capability (at VCC = 3.0 V)
- CMOS low power consumption
- Latch-up performance exceeds 100 mA
- Direct TTL-level interface compatible
- IOFF circuit for partial power-down mode operation
- Unlimited rise and fall times
- Compliant with JEDEC standards: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V, MM JESD22-A115C Class C exceeds 550 V, CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
- Multiple package options
| Qty | Unit Price | Total Amount |
|---|---|---|
| 10+ | $ 0.055 | $ 0.55 |
| 100+ | $ 0.0437 | $ 4.37 |
| 300+ | $ 0.0381 | $ 11.43 |
| 3,000+ | $ 0.0339 | $ 101.70 |
| 6,000+ | $ 0.0305 | $ 183.00 |
| 9,000+ | $ 0.0288 | $ 259.20 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | EnergyMath | |
| Packaging | SOT-363 | |
| Logic Family | 74LVC | |
| Input Type | Schmitt trigger | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | - | |
| Propagation Delay | 2.9ns@4.5V,50pF | |
| Features | Power shutdown protection;Noise suppression function | |
| Input Logic Level - Low | - | |
| Input Logic Level - High | - | |
| Operating Temperature | -40℃~+125℃ | |
| Number of Circuits | 2 | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 4uA | |
| Number of Channels | - | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 10 |
| Multiple | 10 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The EM74LVC2G14 is a dual inverter with Schmitt-trigger inputs. Its inputs can be driven by 3.3 V or 5 V devices. This feature allows the device to be used as a level translator in mixed 3.3 V and 5 V environments. The device is fully specified for partial-power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging backflow current when the device is powered down.
Features
- Wide supply voltage range: 1.65 V to 5.5 V
- Input overvoltage tolerance up to 5.5 V
- High noise immunity
- ±24 mA output drive capability (at VCC = 3.0 V)
- CMOS low power consumption
- Latch-up performance exceeds 100 mA
- Direct TTL-level interface compatible
- IOFF circuit for partial power-down mode operation
- Unlimited rise and fall times
- Compliant with JEDEC standards: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V, MM JESD22-A115C Class C exceeds 550 V, CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
- Multiple package options
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



