LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Cart
EnergyMath EM74LVC2G34GV product image
  • EM74LVC2G34GV thumbnail 1
  • EM74LVC2G34GV thumbnail 2
  • EM74LVC2G34GV thumbnail 3
  • Pinout
  • Footprint
Images for reference only

EnergyMath EM74LVC2G34GVRoHS

Manufacturer
EnergyMathAsian Brands
MPN
EM74LVC2G34GV
LCSC Part #
C49188091
Packaging
SOT-23-6L
Customer #
Key Attributes
Dual buffer gate
Datasheetpdf iconEnergyMath EM74LVC2G34GV
In-Stock: 3,170
3,170 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
10+$ 0.057$ 0.57
100+$ 0.0454$ 4.54
300+$ 0.0396$ 11.88
3,000+$ 0.0352$ 105.60
6,000+$ 0.0317$ 190.20
9,000+$ 0.0299$ 269.10
Standard Packaging3000/Full Reel
Better price for more quantity?
$

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerEnergyMath
PackagingSOT-23-6L
Input typeSchmitt trigger
Voltage - Supply1.65V~5.5V
Output Type-
Current - Output High(IOH)24mA
Series74LVC
Operating Temperature-40℃~+125℃
Current - Output Low(IOL)24mA
Number of Bits per Element1
Channel TypeUnidirectional
FeaturesLevel shifting;Power-off isolation
Number of Elements2
Quiescent Current4uA
Propagation Delay2.5ns@3.3V,50pF
Report an ErrorShow similar products (0) >

Additional Information

TypeDetails
Minimum10
Multiple10
Standard Packaging3000
Sales UnitPiece

Introduction

AI Translation

The EM74LVC2G34 is a dual buffer. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. Schmitt-trigger action on all inputs makes the circuit tolerant of slower input rise and fall times. The device is fully suitable for partial power-down applications using the I_OFF circuit. The I_OFF circuit disables the outputs, preventing damaging backflow current when the device is powered down.

Features

AI Translation
  • Wide supply voltage range: 1.65V to 5.5V
  • Input overvoltage tolerance up to 5.5V
  • High noise immunity
  • ±24 mA output drive capability (at VCC = 3.0 V)
  • CMOS low power consumption
  • Direct TTL-level interface compatible
  • I_OFF circuit for partial power-down mode operation
  • Latch-up performance exceeds 100 mA
  • Compliant with JEDEC standards: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.6 V to 5.5 V)
  • Dual-buffered gate