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RENESAS RC32012A000GN2#BB0 product image
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RENESAS RC32012A000GN2#BB0RoHS

Manufacturer
MPN
RC32012A000GN2#BB0
LCSC Part #
C48580430
Packaging
VFQFN-72(10x10)
Customer #
Key Attributes
FemtoClock Jitter Attenuator and Clock Generator
Datasheetpdf iconRENESAS RC32012A000GN2#BB0

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers
ManufacturerRENESAS
PackagingVFQFN-72(10x10)
Operating Temperature-40℃~+85℃
Clock/OscillatorExternal
Voltage - Supply1.71V~3.465V
Output Frequency(Max)250MHz
Period Jitter, Peak-to-Peak-;-
Phase OffsetSupport
Features-
Output LevelLVCMOS;LVPECL;LVDS;HCSL;CML;SSTL;HSTL
Phase Jitter100fs
Number of Outputs12

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging490
Sales UnitPiece

Introduction

AI Translation

The RC32012A is a fully integrated, low-power, highperformance jitter attenuator and clock generator. The device supports JEDEC JESD204B/C for converter synchronization and SyncE for network-based synchronization. The RC32012A is ideal for providing reference clocks for high-speed serial links up to 28Gbps Ethernet in modular switch line cards and fabric cards in data center equipment, and for clocking data converters in small cell wireless equipment.

Features

AI Translation
  • Can be configured as clock generator or jitter attenuator/synchronizer
  • Low power, less than 1.2W typical
  • Low jitter, less than 100 fs-RMS
  • Compliant with ITU-T G.8262 and G.8262.1 option 1 and 2 for synchronous Ethernet Equipment Clock (EEC/eEEC) without degrading output jitter
  • PCIe Gen 1-6 CC, SRIS and SRNS support
  • Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz
  • Up to four fractional output dividers and 12 integer output dividers
  • Each fractional output divider can be slaved with DPLL or SYS-DPLL or free-run locked to APLL
  • DPLL can be configured as DCO and each fractional output divider can be configured as NCO or DCO
  • Combo bus allows frequency sharing between DPLL, System DPLL, and each of the four fractional output dividers
  • LVCMOS, LVPECL, LVDS, HCSL, CML, SSTL, HSTL output modes supported with programmable output swing and common mode voltage
  • JESD204B/C support on differential or single ended outputs with DC-coupling or AC-coupling
  • Up to seven single-ended or two differential clock inputs, one crystal/XO input, and one XO/TCXO/OCXO input
  • Up to nine GPIO pins programmable to device select or system monitor options
  • Supports 1MHz, 400kHz SMBus, or 50MHz SPI serial port
  • Internal non-volatile memory (up to 16 different configurations), or external serial I2C EEPROM provide default device settings on power-up.
  • 2.5V and 3.3V core and 1.8V, 2.5V, and 3.3V output operation
  • -40℃ to +85℃ industrial temperature operation

Applications

AI Translation
  • Switches / Routers
  • Jitter attenuation for 10 / 25 / 40 / 100 / 200 / 400 Gbps Ethernet PHYs in Switch Line Cards
  • Clock generation for 10 / 25 / 40 / 100 / 200 / 400 Gbps Ethernet PHYs in Switch Fabric Cards
  • Small Cell for 4.5G and 5G
  • Medical Imaging
  • Professional Audio and Video
In-Stock: 3
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QtyUnit PriceTotal Amount
1+$ 55.8601$ 55.86
10+$ 54.1508$ 541.51
Standard Packaging490/Full Reel
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