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TI CD74HC74M96 product image
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TI CD74HC74M96RoHS

Manufacturer
TI
MPN
CD74HC74M96
LCSC Part #
C484719
Packaging
SOIC-14
Customer #
Key Attributes
Dual D Flip-Flop with Set and Reset, Positive-Edge Trigger
Datasheetpdf iconTI CD74HC74M96
In-Stock: 332
332 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.4054$ 0.41
10+$ 0.3227$ 3.23
30+$ 0.2871$ 8.61
100+$ 0.2417$ 24.17
500+$ 0.2222$ 111.10
1,000+$ 0.1914$ 191.40
Standard Packaging2500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Flip Flops
ManufacturerTI
PackagingSOIC-14
Voltage - Supply2V~6V
Number of Bits per Element1
Output TypeComplementary type
Operating Temperature-55℃~+125℃
Series74HC Series
Synchronous/AsynchronousAsynchronous
Number of Elements2
Current - Output High(IOH)5.2mA
Current - Output Low(IOL)5.2mA
Setup Time12ns
Quiescent Current4uA
Hold Time3ns
Propagation Delay30ns@6V,50pF
Trigger TypeRising Edge
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2500
Sales UnitPiece

Introduction

AI Translation
  • Wide Operating Temperature Range... -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types:
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of Vcc at Vcc = 5V
  • HCT Types:
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, I ≤ 1μA at VOL, VOH
  • The ’HC74 and ’HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
  • This flip - flop has independent DATA, SET, RESET and CLOCK inputs and Q and Q̅ outputs. The logic level present at the data input is transferred to the output during the positive - going transition of the clock pulse. SET and RESET are independent of the clock and are accomplished by a low level at the appropriate input.
  • The HCT logic family is functionally as well as pin compatible with the standard LS logic family.

Features

AI Translation
  • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
  • Asynchronous Set and Reset
  • Complementary Outputs
  • Buffered Inputs
  • Typical fMAX = 50MHz at vCC = 5V, cL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)