Corebai Microelectronics CBM99D57BQ
| Manufacturer | Corebai MicroelectronicsAsian Brands |
| MPN | CBM99D57BQ |
| LCSC Part # | C476450 |
| Packaging | TQFP-100-EP(14x14) |
| Customer # | |
| Key Attributes | 14 1.8V~3.3V TQFP-100-EP(14x14) Direct Digital Synthesis (DDS) RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Direct Digital Synthesis (DDS) | |
| Manufacturer | Corebai Microelectronics | |
| Packaging | TQFP-100-EP(14x14) | |
| Resolution (Bits) | 14 | |
| Voltage - Supply | 1.8V~3.3V | |
| The main FCLK | 1GHz | |
| Features | Multi-chip synchronization;Integrated phase-locked loop;Low-power mode;Integrated modulator;Programmable gain control |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 90 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The CBM99D57 enables I/Q modulator and upconverter functions in a variety of high-end communication systems. It integrates a high-speed DDS, a high-speed 14-bit DAC, a clock multiplier circuit, digital filters, and other DSP functions. The device provides baseband upconversion for data transmission in wired or wireless communication systems, delivering excellent performance in terms of speed, power consumption, and spectral performance. It supports 16-bit serial I/Q baseband data input and can be programmed to operate as a single-tone sine wave source or in interpolating DAC mode. The device achieves a high-speed internal sampling clock via an internal oscillator, a high-speed divide-by-2 circuit, and a low-noise PLL.
Features
- Power supply: 1.8 V and 3.3 V
- Internal system clock: 1 GSPS (up to 400 MHz analog output)
- Integrated 1 GSPS 14-bit DAC
- Input data rate: 250 MSPS
- Output phase noise: ≤−124 dBc/Hz (1 kHz offset, 400 MHz carrier)
- Narrowband SFDR: > 80 dB
- 8 programmable profile registers with shift keying support
- Inverse sinc correction filter
- Reference clock multiplication
- Internal oscillator supporting single-crystal operation
- Software/hardware-controlled power-down
- Integrated RAM
- Phase modulation
- Multi-chip synchronization
- Easy interface with Blackfin SPORT
- Configurable interpolation factor: 4 to 252×
- Gain control DAC
- Internal divider supporting reference frequencies up to 2 GHz
- Package: 100-pin TQFP_EP
Applications
- HFC data, voice, and video modems
- Wireless base station transmission
- Broadband communication transmission
- VoIP
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 22.2542 | $ 22.25 |
| 30+ | $ 21.1356 | $ 634.07 |
Standard Packaging90/Full Tray | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Direct Digital Synthesis (DDS) | |
| Manufacturer | Corebai Microelectronics | |
| Packaging | TQFP-100-EP(14x14) | |
| Resolution (Bits) | 14 | |
| Voltage - Supply | 1.8V~3.3V | |
| The main FCLK | 1GHz | |
| Features | Multi-chip synchronization;Integrated phase-locked loop;Low-power mode;Integrated modulator;Programmable gain control |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 90 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The CBM99D57 enables I/Q modulator and upconverter functions in a variety of high-end communication systems. It integrates a high-speed DDS, a high-speed 14-bit DAC, a clock multiplier circuit, digital filters, and other DSP functions. The device provides baseband upconversion for data transmission in wired or wireless communication systems, delivering excellent performance in terms of speed, power consumption, and spectral performance. It supports 16-bit serial I/Q baseband data input and can be programmed to operate as a single-tone sine wave source or in interpolating DAC mode. The device achieves a high-speed internal sampling clock via an internal oscillator, a high-speed divide-by-2 circuit, and a low-noise PLL.
Features
- Power supply: 1.8 V and 3.3 V
- Internal system clock: 1 GSPS (up to 400 MHz analog output)
- Integrated 1 GSPS 14-bit DAC
- Input data rate: 250 MSPS
- Output phase noise: ≤−124 dBc/Hz (1 kHz offset, 400 MHz carrier)
- Narrowband SFDR: > 80 dB
- 8 programmable profile registers with shift keying support
- Inverse sinc correction filter
- Reference clock multiplication
- Internal oscillator supporting single-crystal operation
- Software/hardware-controlled power-down
- Integrated RAM
- Phase modulation
- Multi-chip synchronization
- Easy interface with Blackfin SPORT
- Configurable interpolation factor: 4 to 252×
- Gain control DAC
- Internal divider supporting reference frequencies up to 2 GHz
- Package: 100-pin TQFP_EP
Applications
- HFC data, voice, and video modems
- Wireless base station transmission
- Broadband communication transmission
- VoIP
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



