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TI SN74LVC2T45MDCTTEPRoHS

Manufacturer
MPN
SN74LVC2T45MDCTTEP
LCSC Part #
C465978
Packaging
SM-8
Customer #
Key Attributes
Dual-bit dual-supply bus transceiver with configurable voltage translation and 3-state outputs
Datasheetpdf iconTI SN74LVC2T45MDCTTEP
In-Stock: 372
372 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 2.9698$ 2.97
10+$ 2.6138$ 26.14
30+$ 2.4334$ 73.00
250+$ 2.1896$ 547.40
500+$ 2.1034$ 1051.70
1,000+$ 2.066$ 2066.00
Standard Packaging250/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Translators, Level Shifters
ManufacturerTI
PackagingSM-8
output typeTri-State
Output Signal-
Input Signal-
Operating Temperature-55℃~+125℃
Data Rate420Mbps
Number of Elements1
Channel TypeBidirectional
FeaturesPower-off protection;Output enable high-impedance
Voltage - Supply1.65V~5.5V;1.65V~5.5V
Number of Circuits2

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging250
Sales UnitPiece

Introduction

AI Translation

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess I_CC and I_CCZ. The SN74LVC2T45 is designed so that the DIR input circuit is supplied by V_CCA. This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The V_CC isolation feature ensures that if either V_CC input is at GND, both ports are in the high-impedance state. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Features

AI Translation
  • Available in the NanoFree™ Package
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • V_CC Isolation Feature – If Either V_CC Input Is at GND, Both Ports Are in the High-Impedance State
  • DIR Input Circuit Referenced to V_CCA
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • I_off Supports Partial-Power-Down Mode Operation
  • Max Data Rates:
    • 420 Mbps (3.3-V to 5-V Translation)
    • 210 Mbps (Translate to 3.3 V)
    • 140 Mbps (Translate to 2.5 V)
    • 75 Mbps (Translate to 1.8 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22:
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)