onsemi NB6L295MNG

The NB6L295 is a Dual Channel Programmable Delay Chip designed primarily for Clock or Data de−skewing and timing adjustment. The NB6L295 is versatile in that two individual variable delay channels, PD0 and PD1, can be configured in one of two operating modes, a Dual Delay or an Extended Delay. In the Dual Delay Mode, each channel has a programmable delay section which is designed using a matrix of gates and a chain of multiplexers. There is a fixed minimum delay of 3.2 ns per channel. The Extended Delay Mode amounts to the additive delay of PD0 plus PD1 and is accomplished with the Serial Data Interface MSEL bit set High. This will internally cascade the output of PD0 into the input of PD1. Therefore, the Extended Delay path starts at the IN0/IN0 inputs, flows through PD0, cascades to the PD1 and outputs through Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended Delay Mode. The required delay is accomplished by programming each delay channel via a 3−pin Serial Data Interface, described in the application section. The digitally selectable delay has an increment resolution of typically 11 ps with a net programmable delay range of either 0 ns to 6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the Extended Delay Mode. The Multi−Level Inputs can be driven directly by differential LVPECL, LVDS or CML logic levels; or by single ended LVPECL, LVCMOS or LVTTL. A single enable pin is available to control both inputs. The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295 LVPECL output contains temperature compensation circuitry. This device is offered in a 4 mm x 4 mm 24−pin QFN Pb−free package.

• Input Clock Frequency >1.5 GHz with 550 mV VOUTPP
• Input Data Rate >2.5 Gb/s
• Programmable Delay Range: 0 ns to 6 ns per Delay Channel
• Programmable Delay Range: 0 ns to 11.2 ns for Extended Delay Mode
• Total Delay Range: 3.2 ns to 8.8 ns per Delay Channel
• Total Delay Range: 6 ns to 17 ns in Extended Delay Mode
• Monotonic Delay: 11 ps Increments in 511 Steps
• Linearity ± 20 ps, Maximum
• 100 ps Typical Rise and Fall Times
• 3 ps Typical Clock Jitter, RMS
• 20 ps Pk-Pk Typical Data Dependent Jitter
• LVPECL, CML or LVDS Differential Input Compatible
• LVPECL, LVCMOS, LVTTL Single−Ended Input Compatible
• 3−Wire Serial Interface
• Input Enable/Disable
• Operating Range: VCC = 2.375 V to 3.6 V
• LVPECL Output Level; 780 mV Peak−to−Peak, Typical
• Internal 50 Ω Input Termination Provided
• -40°C to 85°C Ambient Operating Temperature
• 24−Pin QFN, 4 mm x 4 mm
• These are Pb−Free Devices