onsemi MC74VHC74DTR2G
| Manufacturer | |
| MPN | MC74VHC74DTR2G |
| LCSC Part # | C464023 |
| Packaging | TSSOP-14 |
| Customer # | |
| Key Attributes | Dual D-Type Flip-Flop with Set and Reset |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | onsemi | |
| Packaging | TSSOP-14 | |
| Voltage - Supply | 2V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary type | |
| Operating Temperature | -55℃~+125℃ | |
| Series | 74VHC Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 2 | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 5ns | |
| Quiescent Current | 2uA | |
| Hold Time | 500ps | |
| Propagation Delay | 9.3ns@5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The MC74VHC74 is an advanced high speed CMOS D−type flip−flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse. Reset (RD(overline)) and Set (SD(overline)) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
- High Speed: fmax = 170 MHz (Typ) at VCC = 5 V
- Low Power Dissipation: ICC = 2 μA (Max) at TA = 25℃
- High Noise Immunity: VNI = VNIL = 28% VCC
- Power Down Protection Provided on Inputs
- Balanced Propagation Delays
- Designed for 2.0 V to 5.5 V Operating Range
- Low Noise: VOLP = 0.8 V (Max)
- Pin and Function Compatible with Other Standard Logic Families
- Latchup Performance Exceeds 300 mA
- ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V
- Chip Complexity: 128 FETs or 32 Equivalent Gates
- NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.2058 | $ 1.03 |
| 50+ | $ 0.2014 | $ 10.07 |
| 150+ | $ 0.1984 | $ 29.76 |
| 500+ | $ 0.1954 | $ 97.70 |
Standard Packaging2500/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | onsemi | |
| Packaging | TSSOP-14 | |
| Voltage - Supply | 2V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary type | |
| Operating Temperature | -55℃~+125℃ | |
| Series | 74VHC Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 2 | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 5ns | |
| Quiescent Current | 2uA | |
| Hold Time | 500ps | |
| Propagation Delay | 9.3ns@5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The MC74VHC74 is an advanced high speed CMOS D−type flip−flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse. Reset (RD(overline)) and Set (SD(overline)) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
- High Speed: fmax = 170 MHz (Typ) at VCC = 5 V
- Low Power Dissipation: ICC = 2 μA (Max) at TA = 25℃
- High Noise Immunity: VNI = VNIL = 28% VCC
- Power Down Protection Provided on Inputs
- Balanced Propagation Delays
- Designed for 2.0 V to 5.5 V Operating Range
- Low Noise: VOLP = 0.8 V (Max)
- Pin and Function Compatible with Other Standard Logic Families
- Latchup Performance Exceeds 300 mA
- ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V
- Chip Complexity: 128 FETs or 32 Equivalent Gates
- NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



