ST STWD100NYWY3F

The STWD100 watchdog timer circuits are self-contained devices which prevent system failures that are caused by certain types of hardware errors (non-responding peripherals, bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.). The STWD100 watchdog timer has an input, WDl, and an output, WDO（overline）. The input is used to clear the internal watchdog timer periodically within the specified timeout period, twd. While the system is operating correctly, it periodically toggles the watchdog input, WDl. If the system fails, the watchdog timer is not reset, a system alert is generated and the watchdog output, WDO, is asserted. The STWD100 circuit also has an enable pin, EN, which can enable or disable the watchdog functionality. The EN（overline） pin is connected to the internal pull-down resistor. The device is enabled if the EN（overline） pin is left floating. WDO output is available in open drain or push-pull configuration.

• Current consumption 13 μA typ.
• Available watchdog timeout periods are 3.4 ms, 6.3 ms, 102 ms and 1.6 s
• Chip enable input
• Open drain or push-pull WDO output
• Operating temperature range: -40 to +125 °C
• Package SOT23-5, SC70-5 (SOT323-5)
• ESD performance - HBM: 2000 V, RCDM: 1000V

• Telecommunications
• Alarm systems
• Industrial equipment
• Networking
• Medical equipment
• UPS (uninterruptible power supply)