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Nexperia 74LVC8T245PW,118RoHS

Manufacturer
MPN
74LVC8T245PW,118
LCSC Part #
C458788
Packaging
TSSOP-24
Customer #
Key Attributes
8-bit dual supply translating transceiver; 3-state
Datasheetpdf iconNexperia 74LVC8T245PW,118
In-Stock: 1,374
1,374 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.8961$ 0.90
10+$ 0.7182$ 7.18
30+$ 0.6292$ 18.88
100+$ 0.5403$ 54.03
500+$ 0.4869$ 243.45
1,000+$ 0.4594$ 459.40
Standard Packaging2500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerNexperia
PackagingTSSOP-24
Voltage - Supply1.2V~5.5V;1.2V~5.5V
Operating Temperature-40℃~+125℃
Output TypeTri-State
Channel TypeBidirectional
FeaturesPower-off protection;Output enable high-impedance
Number of Elements1
Number of Channels8

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2500
Sales UnitPiece

Introduction

AI Translation

The 74LVC8T245; 74LVCH8T245 are 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a valid logic level.

Features

AI Translation
  • Wide supply voltage range:
    • VCC(A): 1.2 V to 5.5 V
    • VCC(B): 1.2 V to 5.5 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
    • JESD36 (4.5 V to 5.5 V)
  • Maximum data rates:
    • 420 Mbps (3.3 V to 5.0 V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
    • 60 Mbps (translate to 1.5 V)
  • Suspend mode
  • Latch-up performance exceeds 100 mA per JESD 78B Class II
  • ±24 mA output drive (VCC = 3.0 V)
  • Inputs accept voltages up to 5.5 V
  • Low power consumption: 30 μA maximum ICC
  • IOFF circuitry provides partial Power-down mode operation
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 4000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃