MAXIM MAX3421EEHJ+

The MAX3421E USB peripheral/host controller contains the digital logic and analog circuitry necessary to implement a full-speed USB peripheral or a full-/lowspeed host compliant to USB specification rev 2.0. A built-in transceiver features ± 15KV ESD protection and programmable USB connect and disconnect. An internal serial interface engine (SIE) handles low-level USB protocol details such as error checking and bus retries. The MAX3421E operates using a register set accessed by an SPI interface that operates up to 26MHz. Any SPI master (microprocessor, ASIC, DSP, etc.) can add USB peripheral or host functionality using the simple 3- or 4- wire SPI interface. The MAX3421E makes the vast collection of USB peripherals available to any microprocessor, ASIC, or DSP when it operates as a USB host. For point-to-point solutions, for example, a USB keyboard or mouse interfaced to an embedded system, the firmware that operates the MAX3421E can be simple since only a targeted device is supported. Internal level translators allow the SPI interface to run at a system voltage between 1.4V and 3.6V. USB-timed operations are done inside the MAX3421E with interrupts provided at completion so an SPI master does not need timers to meet USB timing requirements. The MAX3421E includes eight general-purpose inputs and outputs so any microprocessor that uses 1/O pins to implement the SPI interface can reclaim the 1/O pins and gain additional ones. The MAX3421E operates over the extended -40°C to +85°C temperature range and is available in a 32-pin TQFP package (5mm×5mm) and a 32-pin TQFN package (5mm×5mm).

• Microprocessor-Independent USB Solution
• Software Compatible with the MAX3420E USB Peripheral Controller with SPI Interface
• Complies with USB Specification Revision 2.0 (Full-Speed 12Mbps Peripheral, Full-/Low-Speed 12Mbps/1.5Mbps Host)
• Integrated USB Transceiver
• Firmware/Hardware Control of an Internal 5+ Pullup Resistor (Peripheral Mode) and D+/D- - Pulldown Resistors (Host Mode)
• Programmable 3- or 4-Wire, 26MHz SPI Interface
• Level Translators and yL Input Allow Independent System Interface Voltage
• Internal Comparator Detects VBUS for SelfPowered Peripheral Applications
• ESD Protection on D+, D-, and VBCOMP
• Interrupt Output Pin (Level- or ProgrammableEdge) Allows Polled or Interrupt-Driven SPI Interface
• Eight General-Purpose Inputs and Eight GeneralPurpose Outputs
• Interrupt Signal for General-Purpose Input Pins, Programmable Edge Polarity
• Intelligent USB SIE
• Automatically Handles USB Flow Control and Double Buffering
• Handles Low-Level USB Signaling Details
• Contains Timers for USB Time-Sensitive Operations so SPI Master Does Not Need to Time Events
• Space-Saving Lead-Free TQFP and TQFN Packages (5mm x 5mm)
• Eleven Registers (R21–R31) are Added to the MAX3420E Register Set to Control Host Operation
• Host Controller Operates at Full Speed or Low Speed
• FIFOS SNDFIFO: Send FIFO, Double-Buffered 64-Byte RCVFIFO: Receive FIFO, Double-Buffered 64-Byte
• Handles DATA0/DATA1 Toggle Generation and Checking
• Performs Error Checking for All Transfers
• Automatically Generates SOF (Full-Speed)/EOP (Low-Speed) at 1ms Intervals
• Automatically Synchronizes Host Transfers with Beginning of Frame (SOF/EOP)
• Reports Results of Host Requests
• Supports USB Hubs
• Supports ISOCHRONOUS Transfers
• Simple Programming SIE Automatically Generates Periodic SOF (Full-Speed) or EOP (Low-Speed) Frame Markers SPI Master Loads Data, Sets Function Address, Endpoint, and Transfer Type, and Initiates the Transfer MAX3421E Responds with an Interrupt and Result Code Indicating Peripheral Response Transfer Request Can be Loaded Any Time SIE Synchronizes with Frame Markers For Multipacket Transfers, the SIE Automatically Maintains and Checks the Data Toggles
• Built-In Endpoint FIFOS EP0: CONTROL (64 bytes) EP1: OUT, BULK or INTERRUPT, 2×64 Bytes (Double-Buffered) EP2: IN, BULK or INTERRUPT, 2×64 Bytes (Double-Buffered) EP3: IN, BULK or INTERRUPT (64 Bytes)
• Double-Buffered Data Endpoints Increase Throughput by Allowing the SPI Master to Transfer Data Concurrent with USB Transfers
• SETUP Data Has its Own 8-Byte FIFO, Simplifying Firmware