Infineon/CYPRESS CY8C4126AXI-S433

PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM Cortex-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4100S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S products will be upward compatible with members of the PSoC 4 platform for new applications and design needs.

• 48-MHz ARM Cortex-M0+ CPU with single-cycle multiply
• Up to 64 KB of flash with Read Accelerator
• Up to 8 KB of SRAM
• Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.
• 12-bit 1-Msps SAR ADC with differential and single-ended modes, and Channel Sequencer with signal averaging
• Single-slope 10-bit ADC function provided by a capacitance sensing block
• Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
• Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs
• Deep Sleep mode with operational analog and 2.5-μA digital system current
• Cypress CapSense Sigma-Delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance
• Cypress-supplied software component makes capacitive sensing design easy
• Automatic hardware tuning (SmartSense™)
• LCD segment drive capability on GPIOs
• Three independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI, or UART functionality
• Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
• Center-aligned, Edge, and Pseudo-random modes
• Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
• Quadrature decoder
• Up to 36 Programmable GPIO Pins
• 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball WLCSP packages
• Any GPIO pin can be CapSense, analog, or digital
• Drive modes, strengths, and slew rates are programmable
• 32-kHz Watch Crystal Oscillator (WCO)
• ±2% Internal Main Oscillator (IMO)
• 32-kHz Internal Low-power Oscillator (ILO)
• Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing)
• Applications Programming Interface (API) component for all fixed-function and programmable peripherals
• After schematic entry, development can be done with ARM-based industry-standard development tools