JSMSEMI SN74HC273PWR-JSM
| Manufacturer | JSMSEMIAsian Brands |
| MPN | SN74HC273PWR-JSM |
| LCSC Part # | C44512760 |
| Packaging | TSSOP-20 |
| Customer # | |
| Key Attributes | TSSOP-20 Flip Flops RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | JSMSEMI | |
| Packaging | TSSOP-20 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 4000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74HC/HCT273 is an 8-bit positive edge-triggered D-type flip-flop with clock (CP) and master reset (MR) inputs. Each output Qn reflects the state of its corresponding Dn input, provided the setup and hold time requirements relative to the low-to-high clock (CP) transition are met. When MR is LOW, all outputs are forced LOW regardless of the clock and data inputs. Input clamping diodes are included, allowing input interfacing to voltages above VCC through current-limiting resistors.
Features
- Shared clock and master reset
- 8-bit rising-edge-triggered D flip-flop
- Operating temperature range: -40℃ to +125℃, Package: DIP20/SOP20/TSSOP20
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.1716 | $ 0.86 |
| 50+ | $ 0.1359 | $ 6.80 |
| 150+ | $ 0.1206 | $ 18.09 |
| 500+ | $ 0.1016 | $ 50.80 |
| 2,500+ | $ 0.0931 | $ 232.75 |
| 4,000+ | $ 0.088 | $ 352.00 |
Standard Packaging4000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | JSMSEMI | |
| Packaging | TSSOP-20 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 4000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74HC/HCT273 is an 8-bit positive edge-triggered D-type flip-flop with clock (CP) and master reset (MR) inputs. Each output Qn reflects the state of its corresponding Dn input, provided the setup and hold time requirements relative to the low-to-high clock (CP) transition are met. When MR is LOW, all outputs are forced LOW regardless of the clock and data inputs. Input clamping diodes are included, allowing input interfacing to voltages above VCC through current-limiting resistors.
Features
- Shared clock and master reset
- 8-bit rising-edge-triggered D flip-flop
- Operating temperature range: -40℃ to +125℃, Package: DIP20/SOP20/TSSOP20
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



