CHIPLON CLM320VC5402PGE100

The CLM320VC5402 fixed-point DSP is based on an enhanced Harvard architecture featuring one program memory bus and three data memory buses. The processor provides a highly parallel ALU, dedicated hardware logic, on-chip memory, and additional on-chip peripherals. The operational flexibility and high-speed technical foundation of this DSP stem from its highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be executed within a single cycle. Instructions with parallel store and application-specific capabilities can fully exploit this architecture. Additionally, data transfers between data and program spaces are supported. This parallelism enables powerful arithmetic, logic, and bit-manipulation operations to be performed within a single machine cycle. Furthermore, the 5402 includes control mechanisms for managing interrupts, repeat operations, and function calls. The CLM320VC5402PGE (144-pin LQFP) package is pin-compatible with the 'LC548, 'LC/VC549, and 'VC5410 devices. The CLM320VC5402GGU (144-pin BGA) package is pin-compatible with the 'LC548 and 'LC/VC549 devices.

• Advanced multi-bus architecture with three independent 16-bit data memory buses and one program memory bus
• 40-bit ALU including a 40-bit barrel shifter and two independent 40-bit accumulators
• 17×17-bit parallel multiplier coupled with a 40-bit dedicated adder for non-pipelined single-cycle MAC operations
• Compare, Select, and Store Unit (CSSU) for accumulate/compare selection of the Viterbi operator
• Exponent encoder computes the exponent value of a 40-bit accumulator in one clock cycle
• Two address generators with eight auxiliary registers and two ARAUs
• Data bus with bus-holder feature
• Extended addressing mode with maximum 1M×16-bit addressable external program space
• 4K×16-bit on-chip ROM
• 16K×16-bit dual-access on-chip RAM
• Single-instruction repeat and block repeat operations for program code
• Block memory move instructions for efficient program and data management
• Instructions with 32-bit long-word operands
• Instructions with 2/3-operand reads
• Arithmetic instructions with parallel store and parallel load
• Conditional store instructions
• Fast return from interrupt
• On-chip peripheral software-programmable wait-state generator and programmable bank switching
• On-chip PLL clock generator with internal oscillator or external clock source
• Two McBSPs
• Enhanced 8-bit parallel HPI8
• Two 16-bit timers
• Six-channel DMA controller
• IDLE1, IDLE2, and IDLE3 instructions with power-down modes for power management
• CLKOUT disable control to turn off CLKOUT
• On-chip scan-based emulation logic, IEEE Std 1149.1 (JTAG) boundary-scan logic
• 10ns single-cycle fixed-point instruction execution (100MIPS) for 3.3V supply (1.8V core)
• Available in 144-pin LQFP (PGE suffix) and 144-pin BGA (GGU suffix)