Nanya Tech NT5AD512M16A4-HR
| Manufacturer | Nanya TechAsian Brands |
| MPN | NT5AD512M16A4-HR |
| LCSC Part # | C428585 |
| Packaging | TFBGA-96 |
| Customer # | |
| Key Attributes | 1.2V 8Gbit 1.333GHz DDR4 SDRAM TFBGA-96 Memory (ICs) RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | Nanya Tech | |
| Packaging | TFBGA-96 | |
| Refresh Current | - | |
| Voltage - Supply | 1.2V | |
| Memory Size | 8Gbit | |
| Operating temperature | 0℃~+95℃ | |
| Clock Frequency | 1.333GHz | |
| Features | Auto self-refresh;Built-in temperature sensor;Auto precharge function;Asynchronous reset function;CRC function;Data mask function;Write leveling function;ZQ calibration function | |
| Memory Format | DDR4 SDRAM | |
| Current - Supply | - |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
- DRAM Access Bandwidth
- Separated IO gating structures by Bank Groups
- Self Refresh Abort
- Fine Granularity Refresh
- Signal Synchronization
- Write Leveling via MR settings1
- Read Leveling via MPR
- Reliability & Error Handling
- Command/Address Parity
- Databus Write CRC
- MPR readout
- Boundary Scan (X16)
- Post Package Repair
- Signal Integrity
- Internal VREFDQ Training
- Read Preamble Training
- Gear Down Mode
- Per DRAM Addressability
- Configurable DS for system compatibility
- Configurable On-Die Termination
- Data bus inversion (DBI)
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 Ω ± 1%)
- Power Saving & Efficiency
- POD with VDDQ termination - Command/Address Latency (CAL) - Maximum Power Saving - Low-power Auto Self Refresh (LPASR)
- Programmable Functions
- Output Driver Impedance (34/48)
- CAS Write Latency (9/10/11/12/14/16/18)
- Additive Latency (0/CL - 1/CL - 2)
- CS to Command Address Latency (3/4/5/6/8)
- Command Address Parity Latency (4/5/6)
- Write Recovery Time (10/12/14/16/18/20/24)
- Burst Type (Sequential/Interleaved)
- RTT_PARK (34/40/48/60/80/120/240)
- RTT_NOM (34/40/48/60/80/120/240)
- RTT_WR (80/120/240)
- Read Preamble (1T/2T)
- Write Preamble (1T/2T)
- Burst Length (BL8/BC4/BC4 or 8 on the fly)
- LPASR (Manual: Normal/Reduced/Extended, Auto:TS)
- Options
- Speed Grade (CL - TRCD - TRP) 2
- 2933 Mbps / 20 - 20 - 20
- 2666 Mbps / 19 - 19 - 19
- 2400 Mbps / 17 - 17 - 17
- Temperature Range (τc)
- Commercial Grade : 0℃ ~ 95℃
- Industrial Grade (-I) : -40℃ ~ 95℃
- Quasi Industrial Grade (-T) : -40℃ ~ 95℃
- VDD/VDDQ/VPP - 1.2V / 1.2V / 2.5V
- Speed Grade (CL - TRCD - TRP) 2
- Package information
- Lead-free RoHS compliance and Halogen-free
Not available now
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | Nanya Tech | |
| Packaging | TFBGA-96 | |
| Refresh Current | - | |
| Voltage - Supply | 1.2V | |
| Memory Size | 8Gbit | |
| Operating temperature | 0℃~+95℃ | |
| Clock Frequency | 1.333GHz | |
| Features | Auto self-refresh;Built-in temperature sensor;Auto precharge function;Asynchronous reset function;CRC function;Data mask function;Write leveling function;ZQ calibration function | |
| Memory Format | DDR4 SDRAM | |
| Current - Supply | - |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
- DRAM Access Bandwidth
- Separated IO gating structures by Bank Groups
- Self Refresh Abort
- Fine Granularity Refresh
- Signal Synchronization
- Write Leveling via MR settings1
- Read Leveling via MPR
- Reliability & Error Handling
- Command/Address Parity
- Databus Write CRC
- MPR readout
- Boundary Scan (X16)
- Post Package Repair
- Signal Integrity
- Internal VREFDQ Training
- Read Preamble Training
- Gear Down Mode
- Per DRAM Addressability
- Configurable DS for system compatibility
- Configurable On-Die Termination
- Data bus inversion (DBI)
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 Ω ± 1%)
- Power Saving & Efficiency
- POD with VDDQ termination - Command/Address Latency (CAL) - Maximum Power Saving - Low-power Auto Self Refresh (LPASR)
- Programmable Functions
- Output Driver Impedance (34/48)
- CAS Write Latency (9/10/11/12/14/16/18)
- Additive Latency (0/CL - 1/CL - 2)
- CS to Command Address Latency (3/4/5/6/8)
- Command Address Parity Latency (4/5/6)
- Write Recovery Time (10/12/14/16/18/20/24)
- Burst Type (Sequential/Interleaved)
- RTT_PARK (34/40/48/60/80/120/240)
- RTT_NOM (34/40/48/60/80/120/240)
- RTT_WR (80/120/240)
- Read Preamble (1T/2T)
- Write Preamble (1T/2T)
- Burst Length (BL8/BC4/BC4 or 8 on the fly)
- LPASR (Manual: Normal/Reduced/Extended, Auto:TS)
- Options
- Speed Grade (CL - TRCD - TRP) 2
- 2933 Mbps / 20 - 20 - 20
- 2666 Mbps / 19 - 19 - 19
- 2400 Mbps / 17 - 17 - 17
- Temperature Range (τc)
- Commercial Grade : 0℃ ~ 95℃
- Industrial Grade (-I) : -40℃ ~ 95℃
- Quasi Industrial Grade (-T) : -40℃ ~ 95℃
- VDD/VDDQ/VPP - 1.2V / 1.2V / 2.5V
- Speed Grade (CL - TRCD - TRP) 2
- Package information
- Lead-free RoHS compliance and Halogen-free
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |



