XBLW SN74LS161N(XBLW)

The SN74LS161 is a synchronous presettable binary counter with internal look-ahead carry. Synchronous operation is achieved by clocking all flip-flops simultaneously on the rising edge of the clock (CP). The counter outputs (Q0 to Q3) can be preset to either HIGH or LOW. When the parallel enable input (PE) is LOW, count operation is inhibited and the data present on the data inputs (D0 to D3) is loaded into the counter on the rising edge of the clock. Preset operation can be performed regardless of the levels of the count enable inputs (CEP and CET). When the master reset input (MR) is LOW, Q0 to Q3 are forced LOW regardless of the levels on pins CP, PE, CET, and CEP (providing an asynchronous clear function). Look-ahead carry simplifies serial cascading of counters. Both CEP and CET must be HIGH for counting to occur. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled produces a HIGH pulse with a duration approximately equal to the HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency of cascaded counters is determined by the propagation delay from CP to TC and the setup time from CEP to CP, according to the following formula: f_max = 1 / (t_P(max)(CP to TC) + TSU(CEP to CP)). Inputs include clamping diodes, allowing the inputs to be connected to voltages exceeding V_CC using current-limiting resistors.

• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Asynchronous reset
• Positive edge-triggered clock
• Operating temperature range: -20°C to +85°C
• Package options: DIP-16 / SOP-16 / TSSOP-16