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Winbond W664GG6RB-06RoHS

Manufacturer
WinbondAsian Brands
MPN
W664GG6RB-06
LCSC Part #
C41866572
Packaging
VFBGA-96(13x7.5)
Customer #
Key Attributes
1.14V~1.26V 4Gbit 1.6GHz DDR4 SDRAM VFBGA-96(13x7.5) Memory (ICs) RoHS
Datasheetpdf iconWinbond W664GG6RB-06
In-Stock: 396
396 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
12+$ 19.7834$ 237.40
120+$ 18.962$ 2275.44
360+$ 17.5391$ 6314.08
1,200+$ 16.2971$ 19556.52
Standard Packaging198/Full Tray
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory (ICs)
ManufacturerWinbond
PackagingVFBGA-96(13x7.5)
Refresh Current2mA
Voltage - Supply1.14V~1.26V
Memory Size4Gbit
Operating temperature0℃~+95℃
Clock Frequency1.6GHz
FeaturesAuto self-refresh;Built-in temperature sensor;Auto precharge function;Asynchronous reset function;Data mask function;Write leveling function;Dynamic on-chip termination;ZQ calibration function;CRC function
Memory FormatDDR4 SDRAM
Current - Supply-

Additional Information

TypeDetails
Minimum12
Multiple12
Standard Packaging198
Sales UnitPiece

Introduction

AI Translation

This product is a DDR4 SDRAM memory device in x16 configuration with a 96-ball VFBGA package. It supports high-speed data transfer and incorporates a wide range of advanced features to optimize system performance and reliability. The device includes a simplified state machine, fundamental read/write operation capabilities, and defines detailed reset and initialization procedures. Its operating modes are configurable via mode registers. Core features include burst length and order control, DLL enable/disable sequences, input clock frequency change adaptation, write leveling adjustment, and multiple temperature-controlled refresh modes. Additionally, it supports fine granularity refresh, multipurpose registers for DQ training, data mask, data bus inversion, ZQ calibration, DQ reference voltage training, per-DRAM addressability, command/address latency mode, CRC, command/address parity, gear-down mode, and programmable preamble and postamble. The device adheres to standard timing definitions for activate, precharge, and read operations.

Features

AI Translation
  • Compliant with DDR4 SDRAM standard
  • x16 data width, 96-ball VFBGA package
  • Programmable burst length and burst order
  • Integrated DLL with switchable modes for different operating conditions
  • Input clock frequency variation support
  • Write leveling for signal integrity optimization
  • Multiple temperature-controlled refresh modes: normal temperature mode (-40℃ ≤ TCASE ≤ 85℃) and extended temperature mode (85℃ ≤ TCASE ≤ 105℃)
  • Fine granularity refresh mode with adjustable refresh rate
  • Multi-purpose registers for DQ training
  • Data mask and data bus inversion (DBI) support
  • ZQ calibration command for output drive and termination resistance optimization
  • DQ reference voltage training
  • Per-DRAM addressability
  • Command address latency mode
  • Integrated CRC for data integrity checking
  • Command address parity with error log readback
  • Gear-down mode
  • Programmable write and read preamble
  • Programmable write and read postamble
  • Standard activate, precharge, and read operation timing compliance