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lingxingic SN74LS191DR(LX)RoHS

Manufacturer
lingxingicAsian Brands
MPN
SN74LS191DR(LX)
LCSC Part #
C41413609
Packaging
SOP-16
Customer #
Key Attributes
Presettable Synchronous 4-bit Binary up/down Counter
Datasheetpdf iconlingxingic SN74LS191DR(LX)
In-Stock: 185
185 In stock, ships now
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QtyUnit PriceTotal Amount
5+$ 0.3059$ 1.53
50+$ 0.2402$ 12.01
150+$ 0.212$ 31.80
500+$ 0.1769$ 88.45
2,500+$ 0.1613$ 403.25
5,000+$ 0.1519$ 759.50
Standard Packaging2500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Counters, Dividers
Manufacturerlingxingic
PackagingSOP-16
Number of Bits per Element4
Voltage - Supply2V~6V
DirectionDown Counter;Up Counter
Trigger TypeRising Edge
TimingSynchronous
Operating Temperature-40℃~+125℃
ResetAsynchronous
Number of Elements1
Propagation Delay21ns
Count Rate36MHz
FeaturesAsynchronous parallel load;Synchronous counting;Multi-mode counting

Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging2500
Sales UnitPiece

Introduction

AI Translation

The SN74LS191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to be preset to any desired value. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is LOW. This operation overrides the counting function. Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The up/down (U /D) input signal determines the direction of counting as indicated in the function table. The CE input may go LOW when the clock is in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also, the U/D input should be changed only when either CE or CP is HIGH. Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches '15' in the count-up-mode. The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This feature simplifies the design of multistage counters. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features

AI Translation
  • Synchronous reversible counting
  • Asynchronous parallel load
  • Count enable control for synchronous expansion
  • Single up/down control input
  • Specified from -40 °C to +125 °C
  • Packaging information: DIP16/SOP16/TSSOP16