Tudi M95M02-DRMN6TP-TUDI

The 95M02 device supports the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8−bit instruction register. Reading data stored in the 95M02 is accomplished by simply providing the READ command and an address. Writing to the 95M02, in addition to a WRITE command, address and data, also requires enabling the device for writing by first setting certain bits in a Status Register. After a high to low transition on the ̅C̅S̅ input pin, the 95M02 will accept any one of the six instructions op−codes and will ignore all other possible 8−bit combinations. The communication protocol follows the timing from Figure 14. The 95M02 features an additional Identification Page (256 bytes) which can be accessed for Read and Write operations when the IPL bit from the Status Register is set to “1”. The user can also choose to make the Identification Page permanent write protected by setting the LIP bit from the Status Register.

• Compatible with the Serial Peripheral Interface (SPI) bus
• Memory array – 2 Mb (256 Kbytes) of EEPROM
• Page size: 256 bytes
• Write Byte Write within 8 ms
• Page Write within 8 ms
• Additional Write lockable page (Identification page)
• Write Protect: quarter, half or whole memory array
• Clock frequency: 5 MHz
• Single supply voltage: 2.8 V to 5.5 V
• Enhanced ESD protection
• More than 4 million Write cycles
• More than 200-year data retention
• Packages – RoHS compliant and halogen-free