Nexperia 74LVC161BQ/S505115

The 74LVC161 is a synchronous presettable binary counter with internal look-ahead carry for high-speed counting applications. Synchronous operation is achieved by clocking all flip-flops simultaneously on the rising edge of the clock (pin CP). The counter outputs (pins Q0 to Q3) can be preset to either a HIGH or LOW level. When the parallel enable input (pin PE) is LOW, counting is inhibited and data from the data inputs (pins D0 to D3) is loaded into the counter on the rising edge of the clock, provided the setup and hold time requirements for PE are met. The preset operation takes place regardless of the levels on the count enable inputs (pins CEP and CET). When the master reset input (pin MR) is LOW, all four flip-flop outputs (pins Q0 to Q3) are set LOW regardless of the levels on pins CP, PE, CET, and CEP, providing an asynchronous clear function. The look-ahead carry simplifies serial cascading of counters. Both count enable inputs (pins CEP and CET) must be HIGH for counting to occur. The CET input is fed forward to enable the terminal count output (pin TC). When enabled, the TC output produces a HIGH pulse with a duration approximately equal to the HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for cascaded counters is determined by tPHL (propagation delay from CP to TC) and tsu (setup time from CEP to CP) according to the following formula: fmax = 1 / (tPHL(max) + tsu) It is a high-performance, low-power, low-voltage silicon gate CMOS device that offers superior performance over most advanced CMOS-compatible TTL families.

• 5 V tolerant inputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Asynchronous reset
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive edge-triggered clock
• Complies with JEDEC standard:
  • JESD8-7A (1.65 V to 1.95 V)
  • JESD8-5A (2.3 V to 2.7 V)
  • JESD8-C/JESD36 (2.7 V to 3.6 V)
• Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
• ESD protection:
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-B exceeds 200 V
  • CDM JESD22-C101E exceeds 1000 V