TI 5962-9221503MRA

The 'FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop's Q output. All outputs are forced low by a low logic level on the MR input. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Function, Pinout, and Drive Compatible With FCT and F Logic
• Reduced VOH (Typically = 3.3V) Versions of Equivalent FCT Functions
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• Ioff Supports Partial-Power-Down Mode Operation
• Matched Rise and Fall Times
• ESD Protection Exceeds JESD 22: 2000-V Human-Body Model (A114-A), 200-V Machine Model (A115-A), 1000-V Charged-Device Model (C101)
• Fully Compatible With TTL Input and Output Logic Levels
• CY54FCT273T 32-mA Output Sink Current, 12-mA Output Source Current
• CY74FCT273T 64-mA Output Sink Current, 32-mA Output Source Current