TI 5962-9314801Q2A

These 8-bit positive-edge-triggered D-type flip-flops with a clock (CLK) input are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.

Data (D) input information that meets the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the common clock-enable (CLKEN) input is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the buffered clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at CLKEN.

• State-of-the-Art EPIC-IIB BiCMOS Design Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical VOLO (Output Ground Bounce) < 1V at VCC = 5V, TH = 25℃
• High-Drive Outputs (-32-mA IoH, 64-mA IoL)
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200pF, R = 0)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

• Buffer and storage register implementation
• Shift registers
• Pattern generators