onsemi MC10186FN
| Manufacturer | |
| MPN | MC10186FN |
| LCSC Part # | C3826388 |
| Packaging | - |
| Customer # | |
| Key Attributes | 6 1 2.5ns Flip Flops |
| Datasheet |  onsemi MC10186FN |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | onsemi | |
| Packaging | - | |
| Number of Bits per Element | 6 | |
| Number of Elements | 1 | |
| Setup Time | 2.5ns | |
| Hold Time | 1.5ns | |
| Propagation Delay | 2.5ns | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive–going Clock transition. Thus, outputs may change only on a positive–going Clock transition. A change in the information present at the data (D) input will not affect the output information any other time due to the master–slave construction of this device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT. RESET ONLY FUNCTIONS WHEN CLOCK IS LOW.
Features
- P_D = 460 mW typ/pkg (No Load)
- f_toggle = 150 MHz (typ)
- tr, t_f = 2.0 ns typ (20%-80%)
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | onsemi | |
| Packaging | - | |
| Number of Bits per Element | 6 | |
| Number of Elements | 1 | |
| Setup Time | 2.5ns | |
| Hold Time | 1.5ns | |
| Propagation Delay | 2.5ns | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive–going Clock transition. Thus, outputs may change only on a positive–going Clock transition. A change in the information present at the data (D) input will not affect the output information any other time due to the master–slave construction of this device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT. RESET ONLY FUNCTIONS WHEN CLOCK IS LOW.
Features
- P_D = 460 mW typ/pkg (No Load)
- f_toggle = 150 MHz (typ)
- tr, t_f = 2.0 ns typ (20%-80%)
Compliance & Export Codes
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |