Nexperia 74LVC573ABX115
| Manufacturer | |
| MPN | 74LVC573ABX115 |
| LCSC Part # | C3756672 |
| Packaging | DHXQFN-20(4.5x2.5) |
| Customer # | |
| Key Attributes | 1.65V~3.6V 8 3.4ns@3.3V,50pF 40uA DHXQFN-20(4.5x2.5) Buffers, Drivers, Receivers, Transceivers RoHS |
| Datasheet |  Nexperia 74LVC573ABX115 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | Nexperia | |
| Packaging | DHXQFN-20(4.5x2.5) | |
| Input type | - | |
| Voltage - Supply | 1.65V~3.6V | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 24mA | |
| Series | 74LVC | |
| Operating Temperature | -40℃~+125℃ | |
| Current - Output Low(IOL) | 24mA | |
| Number of Bits per Element | 8 | |
| Channel Type | - | |
| Features | Output enable;Level shifting;Power-off isolation | |
| Number of Elements | - | |
| Propagation Delay | 3.4ns@3.3V,50pF | |
| Quiescent Current | 40uA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC573A consists of eight D-type transparent latches, each with a separate D-type input and a three-state true output for bus applications. A latch enable (LE) input and an output enable (OE) input are shared by all internal latches. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent — that is, the latch outputs change state each time the corresponding D inputs change. When LE is LOW, the latches store the information that was present at the D inputs one setup time prior to the HIGH-to-LOW transition of LE. When OE (overline) is LOW, the contents of the eight latches are available at the outputs. When OE (overline) is HIGH, the outputs enter a high-impedance OFF state. Operation of the OE (overline) input does not affect the state of the latches. The inputs can be driven by 3.3V or 5V devices. When disabled, the outputs can withstand voltages up to 5.5V. These features allow these devices to be used as translators in mixed 3.3V or 5V applications. The 74LVC573A is functionally identical to the 74LVC373A but has a different pinout.
Features
- 5 V tolerant inputs/outputs, for interfacing with 5 V logic
- Supply voltage range from 1.2 V to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- High-impedance when V_CC = 0 V
- Flow-through pinout architecture
- Complies with JEDEC standard:
- JESD8-7A(1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection:
- HBM JESD22-A114F exceeds 2000V
- MM JESD22-A115-B exceeds 200V
- CDM JESD22-C101E exceeds 1000 V
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 0.1987 | $ 0.20 |
| 200+ | $ 0.0769 | $ 15.38 |
| 500+ | $ 0.0742 | $ 37.10 |
| 1,000+ | $ 0.0729 | $ 72.90 |
Standard Packaging1/Full Bag | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | Nexperia | |
| Packaging | DHXQFN-20(4.5x2.5) | |
| Input type | - | |
| Voltage - Supply | 1.65V~3.6V | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 24mA | |
| Series | 74LVC | |
| Operating Temperature | -40℃~+125℃ | |
| Current - Output Low(IOL) | 24mA | |
| Number of Bits per Element | 8 | |
| Channel Type | - | |
| Features | Output enable;Level shifting;Power-off isolation | |
| Number of Elements | - | |
| Propagation Delay | 3.4ns@3.3V,50pF | |
| Quiescent Current | 40uA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC573A consists of eight D-type transparent latches, each with a separate D-type input and a three-state true output for bus applications. A latch enable (LE) input and an output enable (OE) input are shared by all internal latches. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent — that is, the latch outputs change state each time the corresponding D inputs change. When LE is LOW, the latches store the information that was present at the D inputs one setup time prior to the HIGH-to-LOW transition of LE. When OE (overline) is LOW, the contents of the eight latches are available at the outputs. When OE (overline) is HIGH, the outputs enter a high-impedance OFF state. Operation of the OE (overline) input does not affect the state of the latches. The inputs can be driven by 3.3V or 5V devices. When disabled, the outputs can withstand voltages up to 5.5V. These features allow these devices to be used as translators in mixed 3.3V or 5V applications. The 74LVC573A is functionally identical to the 74LVC373A but has a different pinout.
Features
- 5 V tolerant inputs/outputs, for interfacing with 5 V logic
- Supply voltage range from 1.2 V to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- High-impedance when V_CC = 0 V
- Flow-through pinout architecture
- Complies with JEDEC standard:
- JESD8-7A(1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection:
- HBM JESD22-A114F exceeds 2000V
- MM JESD22-A115-B exceeds 200V
- CDM JESD22-C101E exceeds 1000 V
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |