RENESAS 74ALVCH16600APA

This 18-bit universal bus transceiver is fabricated using advanced dual-metal CMOS technology. The transceiver combines D-type latches with D-type flip-flops, allowing data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be gated by the clock enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, when LEAB is HIGH, the device operates in transparent mode. When LEAB is LOW, A data is latched if CLKAB remains at a HIGH or LOW logic level. If LEAB is LOW, A data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. Output enable OEAB is active LOW. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in a high-impedance state. B-to-A data flow is similar to A-to-B, but uses OEBA, LEBA, CLKBA, and CLKENBA. The ALVCH16600 is designed with ±24mA output drivers. The drivers are capable of driving moderate to heavy loads while maintaining speed performance. The ALVCH16600 features a "bus-hold" function that retains the last state of the input whenever the input enters a high-impedance state. This prevents inputs from floating and eliminates the need for pull-up/pull-down resistors.

• 0.5-micron CMOS technology, typical tsK(0) (output skew) <250ps
• ESD >2000V (per MIL-STD-883, Method 3015); >200V with machine model (C = 200pF, R = 0)
• SSOP (0.635mm pitch), TSSOP (0.50mm pitch), and TVSOP (0.40mm pitch) packages
• Extended commercial temperature range -40°C to +85°C, Vcc = 3.3V ± 0.3V (normal range), Vcc = 2.7V to 3.6V (extended range), Vcc = 2.5V ± 0.2V, CMOS power level (typical quiescent 0.4μW)
• Rail-to-rail output swing for increased noise margin
• High output drive: ±24mA for heavy loads

• 3.3V high-speed systems
• 3.3V and below computing systems