MAXIM 78P7200-IH

The 78P7200 is a single chip line interface IC designed to work with either a 51.84 Mbit/s STS-1, 44.736 Mbit/s DS3 or 34.368 Mbit/s E3 signal. The receiver recovers clock, positive data and negative data from an Alternate Mark Inversion (AMI) signal. The input signal should be B3ZS or HDB3 coded. The transmitter accepts CMOS level logical clock, positive data and negative data and converts them to the AMI signal to drive a 75Ω coaxial cable. Programmable internal Line Buildout (LBO) circuitry eliminates the need for external LBO networks. When the option pins are properly selected, the shape of the transmitted signal through any cable length of 0 to 450 feet complies with the published templates of ANSI T1.102, ITU-T G.703, Bellcore TR-NWT-000499 and GR-253-CORE. The 78P7200 is designed to work with a B3ZS or HDB3 coded signal. The B3ZS or HDB3 encoding and decoding functions are normally included in the framer ICs or can easily be implemented in a PAL.

• Single chip transmit and receive interface for STS-1 (51.84 Mbit/s), E3 (34.368 Mbit/s) or DS3 (44.736 Mbit/s) applications
• On-chip Receive Equalizer
• Unique clock recovery circuit, requires no crystals, tuned components or external clock
• Selectable transmit line buildout (LBO) to accommodate shorter line lengths
• Compliant with ANSI T1.102-1993, Bellcore TR-NWT-000499 and GR-253-CORE, ITU-T G.703 and G.823_1991
• Low-level input signal indication
• Available in a 28 PLCC surface mount package
• -40°C to ±85°C operating range