MOTOROLA XC56302PV66

The DSP56302 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high performance, single-clock-cycle-per-instruction engine providing a two-fold performance increase over Motorola’s popular DSP56000 core, while retaining code compatibility. Significant architectural enhancements in the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and Direct Memory Access (DMA). The DSP56302 offers 66 MIPS using an internal 66 MHz clock at 3.0–3.6 V. The large onchip memories can support wireless infrastructure applications and allow the chip to be used for RAM-based emulation of low-cost ROM-based solutions. The DSP56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low power dissipation, enabling a new generation of wireless, telecommunications, and multimedia products.

• 66 Million Instructions Per Second (MIPS) with a 66 MHz clock @3.0–3.6 V
• Object code compatible with the DSP56000 core
• Highly parallel instruction set
• Data Arithmetic Logic Unit (ALU) Fully pipelined 24x24-bit parallel Multiplier-Accumulator (MAC) 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) – Conditional ALU instructions – 24-bit or 16-bit arithmetic support under software control
• Program Control Unit (PCU) – Position Independent Code (PIC) support Addressing modes optimized for DSP applications (including immediate offsets) On-chip instruction cache controller – On-chip memory-expandable hardware stack – Nested hardware DO loops Fast auto-return interrupts
• Direct Memory Access (DMA) – Six DMA channels supporting internal and external accesses – One-, two-, and three- dimensional transfers (including circular buffering) – End-of-block-transfer interrupts Triggering from interrupt lines and all peripherals
• Phase Lock Loop (PLL) – Allows change of low power Divide Factor (DF) without loss of lock Output clock with skew elimination
• Hardware debugging support – On-Chip Emulation (OnCE) module Joint Action Test Group (JTAG) Test Access Port (TAP) Address Trace mode reflects internal accesses at the external port
• Program RAM, Instruction Cache, X data RAM, and Y data RAM size is programmable
• 192 x 24-bit bootstrap ROM
• Data memory expansion to two 256 Kx24-bit word memory spaces (or up to two 4 Mx24-bit word memory spaces by using the Address Attribute AA0– AA3 signals) Program memory expansion to one 256 Kx24-bit words memory space (or up to one 4 Mx24-bit word memory space by using the Address Attribute AA0– AA3 signals)
• External memory expansion port
• Chip Select Logic for glueless interface to SRAMs
• On-chip DRAM Controller for glueless interface to DRAMs
• Enhanced DSP56000-like 8-bit parallel Host Interface (HI08) supports a variety of buses (e.g., ISA) and provides glueless connection to a number of industry standard microcomputers, microprocessors, and DSPs
• Two Enhanced Synchronous Serial Interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater)
• Serial Communications Interface (SCI) with baud rate generator
• Triple timer module
• Up to thirty-four programmable General Purpose Input/Output (GPIO) pins, depending on which peripherals are enabled
• Very low power CMOS design
• Wait and Stop low power standby modes
• Fully-static logic, operation frequency down to 0 Hz (DC)
• Optimized power management circuitry (instruction-dependent, peripheraldependent, and mode-dependent)

• wireless infrastructure applications
• RAM-based emulation for low-cost ROM-based solutions