ADI ADSP-2186BSTZ-115

The ADSP-2186 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2186 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-2186 integrates 40K bytes of on-chip memory configured as 8K words (24-bit) of program RAM and 8K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2186 is available in 100-lead LQFP and 144-Ball Mini-BGA packages. In addition, the ADSP-2186 supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2186 operates with a 25 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2186’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2186 can: • Generate the next program address • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation This takes place while the processor continues to: • Receive and transmit data through the two serial ports • Receive and/or transmit data through the internal DMA port • Receive and/or transmit data through the byte DMA port • Decrement timer

• 25 ns Instruction Cycle Time 40 MIPS Sustained Performance
• Single-Cycle Instruction Execution
• Single-Cycle Context Switch
• 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle
• Multifunction Instructions
• Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power-Down Condition
• Low Power Dissipation in Idle Mode
• ADSP-2100 Family Code Compatible, with Instruction Set Extensions
• 40K Bytes of On-Chip RAM, Configured as 8K Words On-Chip Program Memory RAM and 8K Words On-Chip Data Memory RAM
• Dual Purpose Program Memory for Both Instruction and Data Storage
• Independent ALU, Multiplier/Accumulator and Barrel Shifter Computational Units
• Two Independent Data Address Generators
• Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution
• Programmable 16-Bit Interval Timer with Prescaler
• 100-Lead LQFP and 144-Ball Mini-BGA
• 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory (Mode Selectable)
• 4 MByte Byte Memory Interface for Storage of Data Tables and Program Overlays
• 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable)
• I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable)
• Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design (Mode Selectable)
• Programmable Wait State Generation
• Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering