ADI ADSP-2115KST-80

16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter Single-Cycle Instruction Execution & Multifunction Instructions On-Chip Program Memory RAM or ROM & Data Memory RAM Integrated I/O Peripherals: Serial Ports, Timer, Host Interface Port (ADSP-2111 Only)

The ADSP-2100 Family processors are single-chip microcomputers optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-21xx processors are all built upon a common core. Each processor combines the core DSP architecture—computation units, data address generators, and program sequencer—with differentiating features such as on-chip program and data memory RAM, a programmable timer, one or two serial ports, and, on the ADSP-2111, a host interface port.

Fabricated in a high speed, submicron, double-layer metal CMOS process, the highest-performance ADSP-21xx processors operate at 25 MHz with a 40 ns instruction cycle time. Every instruction can execute in a single cycle. Fabrication in CMOS results in low power dissipation.

The ADSP-2100 Family’s flexible architecture and comprehensive instruction set support a high degree of parallelism. In one cycle the ADSP-21xx can perform all of the following operations:

• Generate the next program address • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computation

• Receive and transmit data via one or two serial ports • Receive and/or transmit data via the host interface port (ADSP-2111 only)

The ADSP-2101, ADSP-2105, and ADSP-2115 comprise the basic set of processors of the family. Each of these three devices contains program and data memory RAM, an interval timer, and one or two serial ports. The ADSP-2103 is a 3.3 volt power supply version of the ADSP-2101; it is identical to the ADSP-2101 in all other characteristics.

The ADSP-2111 adds a 16-bit host interface port (HIP) to the basic set of ADSP-21xx integrated features. The host port provides a simple interface to host microprocessors or microcontrollers such as the 8031, 68000, or ISA bus.

• 25 MIPS, 40 ns Maximum Instruction Rate
• Separate On-Chip Buses for Program and Data Memory
• Program Memory Stores Both Instructions and Data (Three-Bus Performance)
• Dual Data Address Generators with Modulo and Bit-Reverse Addressing
• Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup
• Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory (e.g., EPROM )
• Double-Buffered Serial Ports with Companding Hardware, Automatic Data Buffering, and Multichannel Operation
• ADSP-2111 Host Interface Port Provides Easy Interface to 68000, 80C51, ADSP-21xx, Etc.
• Automatic Booting of ADSP-2111 Program Memory Through Host Interface Port
• Three Edge- or Level-Sensitive Interrupts
• Low Power IDLE Instruction
• PGA, PLCC, PQFP, and TQFP Packages
• MIL-STD-883B Versions Available