TI TMS320C6202GJL250X

The TMS320C6202 and TMS320C6202B devices are part of the TMS320C62x™ fixed-point DSP generation in the TMS320C6000™ DSP platform. The C62x™ DSP devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The TMS320C62x™ DSP offers cost-effective solutions to high-performance DSP-progr

• High-Performance Fixed-Point Digital Signal Processors (DSPs)
• 5-, 4-, 3.33-ns Instruction Cycle Time
• 200-, 250-, 300-MHz Clock Rate
• Eight 32-Bit Instructions/Cycle
• 1600, 2000, 2400 MIPS
• C6202 and C6203B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package
• C6202B and C6203B GNZ and GNY Packages are Pin-Compatible
• VelociTI™ Advanced Very-Long-InstructionWord (VLIW) C62x™ DSP Core
• Eight Highly Independent Functional Units: Six ALUs (32-/40-Bit), Two 16-Bit Multipliers (32-Bit Result)
• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Instruction Set Features: Byte-Addressable (8-, 16-, 32-Bit Data), 8-Bit Overflow Protection, Saturation, Bit-Field Extract, Set, Clear, Bit-Counting, Normalization
• 3M-Bit On-Chip SRAM: 2M-Bit Internal Program/Cache (64K 32-Bit Instructions), 1M-Bit Dual-Access Internal Data (128K Bytes), Organized as Two 64K-Byte Blocks for Improved Concurrency
• 32-Bit External Memory Interface (EMIF): Glueless Interface to Synchronous Memories: SDRAM or SBSRAM, Glueless Interface to Asynchronous Memories: SRAM and EPROM, 52M-Byte Addressable External Memory Space
• Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
• Flexible Phase-Locked-Loop (PLL) Clock Generator
• 32-Bit Expansion Bus (XBus): Glueless/Low-Glue Interface to Popular PCI Bridge Chips, Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses, Master/Slave Functionality, Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals
• Three Multichannel Buffered Serial Ports (McBSPs): Direct Interface to T1/E1, MVIP, SCSA Framers, ST-Bus-Switching Compatible, Up to 256 Channels Each
• AC97-Compatible Serial-Peripheral Interface (SPI) Compatible (Motorola™)
• Two 32-Bit General-Purpose Timers
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• 3.3-V I/Os, 1.8-V Internal (C6202); 3.3-V I/Os, 1.5-V Internal (C6202B)

• Multi-channel and multi-function applications
• Three multi-channel buffered serial ports (McBSPs)
• Two 32-bit general-purpose timers
• 32-bit extended bus (XBus) with interface support for synchronous or asynchronous industry-standard host bus protocols
• Glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM as well as asynchronous peripherals