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TI TAS3202PAGR product image
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TI TAS3202PAGRRoHS

Manufacturer
MPN
TAS3202PAGR
LCSC Part #
C3587681
Packaging
TQFP-64(10x10)
Customer #
Key Attributes
TQFP-64(10x10) DSP (Digital Signal Processors) RoHS
Datasheetpdf iconTI TAS3202PAGR
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QtyUnit Price(Reference Only)Total Amount
1+$ 12.3232$ 12.32
200+$ 4.7695$ 953.90
500+$ 4.6014$ 2300.70
1,000+$ 4.5181$ 4518.10
Standard Packaging1500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/DSP (Digital Signal Processors)
ManufacturerTI
PackagingTQFP-64(10x10)
FeaturesHardware MAC acceleration;Integrated ADC interface;High-speed peripheral interface;Low-power mode

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging1500
Sales UnitPiece

Introduction

AI Translation

The TAS3202 is an audio system-on-a-chip (SOC) designed for mini/micro systems, multimedia-speaker, and MP3 player docking systems. It includes analog interface functions: two multiplex (MUX) stereo inputs with one stereo analog-to-digital converter (ADC) and one stereo digital-to-analog converter (DAC) with analog outputs consisting of differential stereo line drivers. Four channels of serial digital audio processing are also provided. The TAS3202 has a programmable audio digital signal processor (DSP) that preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single-cycle 28×48-bit multiplier. The programmability feature allows users to customize features in the DSP RAM. The TAS3202 is composed of eight functional blocks:

  • Analog input/mux/stereo ADC
  • Stereo DAC
  • Analog reference system
  • Power supply
  • Clocks, digital PLL, and serial data interface
  • I2C control interface
  • 8051 microcontroller
  • Audio DSP – digital audio processing

Features

AI Translation
  • High-Quality Audio Performance: 102-dB Analog-to-Digital Converter (ADC)/105-dB Digital-to-Analog Converter (DAC) (Typical) DNR
  • Two Differential Stereo Analog Inputs Multiplexed to One Stereo Input ADC
  • One Differential Stereo Output DAC
  • Two Serial Audio Inputs (Four Channels) and Two Serial Audio Outputs (Four Channels)
  • 135-MHz Maximum Speed, >2812 Total Processing Cycles Per Sample at 48 kHz (2000 Available for Application Code)
  • 512×Fs XTAL Input in Master Mode, 512×Fs MCLK_IN in Slave Mode
  • 48-kHz Sample Rate in Clock Master Mode
  • 44.1-kHz or 48-kHz Sample Rate in Clock Slave Mode
  • 48-Bit Data Path and 28-Bit Coefficients
  • 768 Words of 48-Bit Data Memory
  • 1022 Words of 28-Bit Coefficient Memory
  • 3K Words of 55-Bit Program RAM
  • Hardware Single-Cycle Multiplier (28×48)
  • 5.88K Words of 24-Bit Delay Memory (122.5 ms at 48 kHz)
  • Data Formats: Left Justified, Right Justified, and I²S
  • Two I²C Ports for Slave/Master Download
  • Single 3.3-V Power Supply

Applications

AI Translation
  • MP3 Docking Systems
  • Digital Televisions
  • Mini-Component Audio