onsemi MC74HC595ADR

The MC74HC595A/MC74HCT595A consists of an 8-bit shift register and an 8-bit D-type latch with 3-state parallel outputs. The shift register accepts serial data and provides serial output, while also supplying parallel data to the 8-bit latch. The shift register and latch have separate clock inputs, and the device also features an asynchronous reset for the shift register. The device can interface directly with the SPI serial data ports on CMOS microprocessors and microcontrollers. The MC74HC595A device inputs are compatible with standard CMOS outputs and, with pull-up resistors, are also compatible with TTL outputs. The MC74HCT595A device inputs are compatible with standard CMOS or TTL outputs.

• Output drive capability: 15 low-power Schottky TTL loads
• Outputs directly interface with CMOS, NMOS, and TTL
• Operating voltage range: 2.0 to 6.0V (HC), 4.5 to 5.5V (HCT)
• Low input current: 1.0μA
• High noise immunity characteristic of CMOS devices
• Meets requirements of JEDEC Standard No. 7A
• Chip complexity: 328 FETs or 82 equivalent gates
• Improvements over HC595/HCT595
  • Improved propagation delay
  • 50% reduction in quiescent power consumption
  • Improved input noise and latch-up immunity
• -Q suffix for automotive and other applications requiring unique site and control change requirements; AEC-Q100 qualified with PPAP capability
• These devices are lead-free, halogen-free, and RoHS compliant