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Lattice OR3T1256BA352-DB

Manufacturer
Lattice
MPN
OR3T1256BA352-DB
LCSC Part #
C3292520
Packaging
PBGA-352(35x35)
Customer #
Key Attributes
6272 PBGA-352(35x35) FPGAs (Field Programmable Gate Array)
Datasheetpdf iconLattice OR3T1256BA352-DB

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array)
ManufacturerLattice
PackagingPBGA-352(35x35)
Embedded Block RAM102400bit
Voltage - Supply(VCCIO)-
Number of Logic Elements/Blocks6272
Logic Array Blocks-
Operating Temperature0℃~+70℃
Type-
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging1
Sales UnitPiece

Features

AI Translation
  • High-performance, cost-effective, 0.35 μm (OR3C) and 0.3̆ μm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in 0.3 μm).
  • Same basic architecture as lower-voltage, advanced process technology Series 3 architectures. (See ORCA Series 3L FPGA documentation.)
  • Up to 186,000 usable gates.
  • Up to 342 user I/Os. (OR3Txxx I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.)
  • Pin selectable I/O clamping diodes provide 5 V or 3.3 V PCI compliance and 5 V tolerance on OR3Txxx devices.
  • Twin-quad programmable function unit (PFU) architecture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU.
  • Nine user registers per PFU, one following each LUT, plus one extra. All have programmable clock enable and local set/reset, plus a global set/reset that can be disabled per PFU.
  • Flexible input structure (FINS) of the PFUs provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs. Fast-carry logic and routing to adjacent PFUs for nibble-, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU for up to 40% speed improvement. Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder, and PAL*-like AND-OR with optional INVERT in each programmable logic cell (PLC), with over 50% speed improvement typical.
  • Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementations and less routing delay. TTL or CMOS input levels programmable per pin for the OR3Cxx (5.0 V) devices. Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source. Built-in boundary scan (IEEE †1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins. Enhanced system clock routing for low skew, high-speed clocks originating on-chip or at any I/O. Up to four ExpressCLK inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. StopCLK feature to glitchlessly stop/start ExpressCLKs independently by user command.
  • Programmable I/O (PIO) has: Fast-capture input latch and input flip-flop (FF) latch for reduced input setup time and zero hold time. Capability to (de)multiplex I/O signals. Fast access to SLIC for decodes and PAL-like functions. Output FF and two-signal function generator to reduce CLK to output propagation delay. — Fast open-drain dive capability — Capability to register 3-state enable signal.
  • Baseline FPGA family used in Series 3+ FPSCs (field programmable system chips) which combine FPGA logic and standard cell logic on one device.
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