Lattice OR4E02-3BA352C

Built on the Series 4 reconfigurable embedded system-on-a-chip (SoC) architecture, Lattice introduces its new family of generic Field-Programmable Gate Arrays (FPGAs). The high-performance and highly versatile architecture brings a new dimension to bringing network system designs to market in less time than ever before. This new device family offers many new features and architectural enhancements not available in any earlier FPGA generations. Bringing together highly flexible SRAM-based programmable logic, powerful system features, a rich hierarchy of routing and interconnect resources, and meeting multiple interface standards, the Series 4 FPGA accommodates the most complex and high-performance intellectual property (IP) network designs.

• High-performance platform design:
  • 0.16 μm 7-level metal technology.
  • Internal performance of >250 MHz
  • I/O performance of >420 MHz.
  • Meets multiple I/O interface standards.
  • 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
• Traditional I/O selections:
  • LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os.
  • Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
  • Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
  • Two slew rates supported (fast and slew-limited).
  • Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and zero hold time.
  • Fast open-drain drive capability.
  • Capability to register 3-state enable signal.
  • Off-chip clock drive capability.
  • Two-input function generator in output path.
• New programmable high-speed I/O:
  • Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, and IV), ZBT, and DDR.
  • Double-ended: LDVS, bused-LVDS, and LVPECL.
  • Programmable (on/off) internal parallel termination (100 Ω) also supported for these I/Os.
• New capability to (de)multiplex I/O signals:
  • New double data rate on both input and output at rates up to 350 MHz (700 MHz effective rate).
  • New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
• Enhanced twin-quad programmable function unit (PFU):
  • Eight 16-bit look-up tables (LUTs) per PFU.
  • Nine user registers per PFU, one following each LUT and organized to allow two nibbles to act independently, plus one extra for arithmetic operations.
  • New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects.
  • New LUT structure allows flexible combinations o LUT4, LUT5, new LUT6, 4 to 1 MUX, new 8 to 1 MUX, and ripple mode arithmetic functions in the same PFU.
  • 32x4 RAM per PFU, configurable as single- or dual-port.
  • Create large, fast RAM/ROM blocks (128x8 in only eight PFUs) using the SLIC decoders as bank drivers.
  • Soft-wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU