Lattice LC5512B-75F484C

The ispMACH 5000B represents Lattice's next-generation SuperWIDE CPLD architecture. Through its 68-input wide input block, these devices deliver significantly improved speed performance in typical designs compared to architectures with fewer inputs. In addition to the unique advantages of the SuperWIDE architecture, the ispMACH 5000B incorporates sysIO functionality to support a wide range of advanced I/O standards. The ispMACH 5000B devices consist of multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks (GLBs) interconnected through a single-layer routing system called the Global Routing Pool (GRP). Together, the GLBs and GRP enable designers to implement large designs within a single device without compromising performance. Each GLB has 68 inputs from the GRP and contains 163 product terms. These product terms form groups of five product term clusters, providing inputs directly to the product term sharing array and macrocells. The ispMACH 5000B allows up to 35 product terms to be connected to a single macrocell through the product term sharing array. The macrocells are designed to provide flexible clocking and control functions, with the ability to select among global, product term, and block-level resources. Macrocell outputs feed back into the switch matrix and, where required, into the sysIO cells. All I/Os in the ispMACH 5000B family feature sysIO functionality and are divided into four banks. Each bank has independent I/O power and reference voltages. The sysIO cells allow operation under a wide variety of today's emerging interface standards. Within a bank, inputs can be configured for multiple standards as long as the reference voltage requirements of the selected standards are compatible. Within each bank, outputs can be configured for different standards as long as the I/O power requirements of the selected standards are compatible. Support for such a broad range of standards enables designers to significantly improve board-level performance compared to more traditional LVCMOS standards. The ispMACH 5000B family of in-system programmable (ISP™) high-density programmable logic devices is based on a GLB and GRP architecture, where the GRP connects the GLBs. The GLB outputs drive the GRP. Enhanced switching resources are provided to enable signals in the GRP to drive any or all GLBs. This mechanism allows fast, efficient connectivity throughout the device. Each GLB contains 32 macrocells and a fully populated programmable AND array with 160 logic product terms and three GLB-level control product terms. The GLB has 68 inputs from the GRP, with each product term available in both true and complement form. The three control product terms are used for shared reset, clock, and output enable functions. The programmable AND array consists of 68 inputs and 163 output product terms. The 68 inputs from the GRP are used to form 136 lines (true and complement forms of the inputs) within the AND array. Each line in the array can be wire-ANDed to any of the 163 output product terms. Each of the 160 logic product terms provides input to the dual OR array, while the remaining three control product terms provide inputs for the shared PT clock, shared PT reset, and shared PT output enable, respectively. The 160 logic product terms are grouped in clusters of five, starting from PT0, to form a product term cluster. Each macrocell in the GLB has one product term cluster. In addition to the three control product terms, the first, third, fourth, and fifth product terms of each cluster can be used as PTOE (for output macrocells only), PT clock, PT preset, and PT reset, respectively. Each macrocell in the GLB has two OR gates, referred to as the PTSA OR gate and the PTSA bypass OR gate. The PTSA bypass OR gate receives its five inputs from the combination of product terms associated with the product term cluster. The PTSA bypass OR gate feeds directly into the macrocell for fast, narrow logic. The PTSA OR gate receives its inputs from the combination of product terms associated with the product term cluster. The Product Term Sharing Array (PTSA) consists of 32 inputs from the dual OR array and 32 outputs connected directly to the macrocells. Each output is the OR of any combination of the seven PTSA OR terms connected to that output.

• SuperWIDE 68-input logic block
• Up to 35 product terms per output
• Single-tier global routing pool (GRP)
• LVCMOS 1.8, 2.5, and 3.3
• LVTTL
• SSTL 2 (I and II)
• SSTL 3 (I and II)
• CTT 3.3, CTT 2.5
• HSTL (I and III)
• PCI 3.3
• GTL+
• AGP - 1X
• LVDS (clock input)
• LVPECL (clock input)
• Programmable drive strength
• Product term sharing
• Extensive clock and output enable features
• 128 to 512 macrocells
• 92 to 256 I/Os
• TQFP, PQFP, and fpBGA packages, 128 to 484 pins/balls
• Commercial and industrial temperature ranges
• 2.5V supply
• Hot-plug capability
• Input pull-up, pull-down, or bus-hold (pin-by-pin selectable)
• Open-drain capability
• Macrocell-based power management
• IEEE 1149.1 boundary scan test compliant
• IEEE 1532 in-system programmable (ISP™)