Lattice PALCE22V10Q-25PC/4

The PALCE22V10 provides user-programmable logic to replace conventional SSI/MSI gates and flip-flops with fewer ICs. The PALCE22V10Z is an advanced PAL device manufactured using zero-power, high-speed, electrically erasable CMOS technology. It provides user-programmable logic to replace conventional zero-power CMOS SSI/MSI gates and flip-flops with fewer ICs. The PALCE22V10Z features zero standby power and high-speed performance. With a maximum standby current of 30 μA, the PALCE22V10Z enables extended battery-powered operation. PAL devices implement the common Boolean logic transfer function — sum of products. A PAL device consists of a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums the selected terms at the outputs. Product terms are distributed in quantities ranging from 8 to 16 and connected to the fixed OR array across the various outputs. The OR sum of products feeds into output macrocells. Each macrocell can be programmed as registered or combinatorial, and as active-high or active-low. The output configuration is determined by two bits that control two multiplexers within each macrocell. The PALCE22V10 allows system engineers to implement designs on-chip by programming the EE cells to configure AND and OR gates within the device according to the required logic functions. Complex interconnections between gates that previously required time-consuming board layout are transferred from the PCB to silicon, where they can be easily modified during prototyping or production. The PALCE22V10Z is the zero-power version of the PALCE22V10. It incorporates all the architectural features of the PALCE22V10. In addition, the PALCE22V10Z offers zero standby power and unused product term disable functionality. A product term with all connections removed presents a logic-high state; a product term connected to both the true and complement of any single input presents a logic-low state. The PALCE22V10 has 12 inputs and 10 I/O macrocells. Macrocells allow one of four possible output configurations: registered output or combinatorial I/O, active-high or active-low. Configuration selection is made according to the user's design specifications and the programming of the corresponding configuration bits S₀–S₁. Multiplexer control is connected to ground (0) via a programmable bit, selecting the "0" path through the multiplexer. Erasing the bit disconnects the control line from ground and drives it high, selecting the "1" path. The device has an EE cell link at each input of the AND gate array; connections can be selectively removed by applying appropriate voltages to the circuit. Using easily implemented programming algorithms, these products can be quickly programmed to any custom pattern. The PALCE22V10 has twelve dedicated input lines, and each macrocell output can serve as an I/O pin. Input buffers have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be connected to VCC or ground. Each macrocell of the PALCE22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop loads data on the low-to-high transition of the clock input. In the registered configuration (S₁ = 0), the array feedback comes from the Q̅ of the flip-flop. Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S₁ = 1). In the combinatorial configuration, feedback comes from the pin. Each output has a three-state output buffer with three-state control. A product term controls this buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional I/O pin, which can be configured as a dedicated input if the buffer is permanently disabled. The polarity of each macrocell output can be active-high or active-low, both to satisfy output signal requirements and to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or complement) while the output can still be the desired polarity. It also eliminates the need for De Morgan's transformations. The selection is controlled by programmable bit S₀ in the output macrocell and affects both registered and combinatorial outputs. Selection is made automatically based on design specifications and pin definitions.

• As fast as 5 ns propagation delay and 142.8 MHz fMAX (external)
• Low-power EE CMOS
• 10 macrocells programmable as registered or combinatorial, and active-high or active-low to meet application requirements
• Variable product term distribution allows up to 16 product terms per output for complex functions
• PCI compliant (-5 / -7 / -10)
• Global asynchronous reset and synchronous preset for initialization
• Power-on reset for initialization, register preload for testability
• Broad third-party software and programmer support
• 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC packages
• 5 ns and 7.5 ns versions feature split lead frame for improved performance