Intel/Altera EPM7032STC44-7

The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. The MAX 7000E devices have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate. In-system programmable MAX 7000 devices called MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. The MAX 7000 architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. The MAX 7000 architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices are available in a wide range of packages, including PLCC, PGA, PQFP, RQFP, and TQFP packages. MAX 7000 devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. MAX 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and highspeed parallel expander product terms to provide up to 32 product terms per macrocell.

• High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX architecture
• 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices ISP circuitry compatible with IEEE Std. 1532
• Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
• Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
• Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates
• 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
• PCI-compliant devices available
• Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
• Programmable power-saving mode for a reduction of over 50% in each macrocell
• Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
• 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
• Programmable security bit for protection of proprietary designs
• 3.3-V or 5.0-V operation
• MultiVoltTM I/O interface operation, allowing devices to interface with 3.3–V or 5.0–V devices (MultiVolt I/O operation is not available in 44-pin packages)
• Pin compatible with low-voltage MAX 7000A and MAX 7000B devices
• Enhanced features available in MAX 7000E and MAX 7000S devices: Six pin- or logic-driven output enable signals, Two global clock signals with optional inversion, Enhanced interconnect resources for improved routability, Fast input setup times provided by a dedicated path from I/O pin to macrocell registers, Programmable output slew-rate control
• Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations
• Additional design entry and simulation support provided by EDIF 200 and 300 netlist files, library of parameterized modules (LPM), Verilog HDL, ΔVHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest
• Programming support: Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices. The BitBlasterTM serial download cable, ByteBlasterMVTM parallel port download cable, and MasterBlasterTM serial/universal serial bus (USB) download cable program MAX 7000S devices