The PAL20X10A Series offers Exclusive-OR gates preceding each flip-flop. The XOR gate combines two sum terms, each composed of two product terms. This extra level of logic is very efficient for counter applications.
The combinatorial member of the family, the PAL20L10, offers three product terms per output with no xOR gate. A fourth product term provides the enable term. While the registered devices are offered in only one performance option, the 20L10 is offered in four performance grades.
The family utilizes advanced bipolar process and fuse-link technology. The devices provide user-programmable logic for replacing conventional SSi/MSl gates and flip-flops at a reduced chip count.
The family allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time-consuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production.
The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. In addition, the PAL device provides the following options:
- Variable input/output pin ratio
- Programmable three-state outputs
- Registers with feedback
Product terms with all fuses opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. Registers consist of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock. Unused input pins should be tied to Vcc or GND.
The entire PAL device family is supported by the PALASM software package. The PAL family is programmed on conventional PAL device programmers with appropriate personality and socket adapter modules. Once the PAL device is programmed and verified an additional fuse may be opened to prevent pattern readout. This feature secures proprietary circuits.
Four different devices are available in the 20X10 Series, including both registered and combinatorial devices. All parts are produced with a fuse link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-implemented programming algorithm, these products can be rapidly programmed to any customized pattern. Extra test words are pre-programmed during manufacturing to ensure extremely high field programming yields, and provide extra test paths to achieve excellent parametric correlation.
AMD AMPAL20L10ALJC