lingxingic SN74HC190N(LX)

The SN74HC/HCT190 are asynchronously presettable up/down BCD decade counters. They contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is LOW. As indicated in the function table, this operation overrides the counting function. Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The up/down (U /D) input signal determines the direction of counting as indicated in the function table. The CE input may go LOW when the clock is in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also, the U/D input should be changed only when either CE or CP is HIGH. Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches “9” in the count-up-mode. The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This feature simplifies the design of multistage counters.

• Input levels: For SN74HC190: CMOS level For SN74HCT190: TTL level
• Synchronous reversible counting
• Asynchronous parallel load
• Count enable control for synchronous expansion
• Single up/down control input
• Specified from -40℃ to +125℃
• Packaging information: DIP16/SOP16/TSSOP16