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EDA ModelsEasyEDA
Intel/Altera FW21154AE
| Manufacturer | |
| MPN | FW21154AE |
| LCSC Part # | C3247599 |
| Packaging | PBGA-304(31x31) |
| Customer # | |
| Key Attributes | PBGA-304(31x31) Signal Buffers, Repeaters, Splitters |
| Datasheet |  Intel/Altera FW21154AE |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Signal Buffers, Repeaters, Splitters | |
| Manufacturer | Intel/Altera | |
| Packaging | PBGA-304(31x31) | |
| Features | Address translation and window mapping;Error detection;Plug-and-play and power-on state management;Clock management;Protocol bridging |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Fully compliant with PCI Local Bus Specification Revision 2.1
- Fully compliant with PCI Power Management Specification Version 1.0
- Supports 64-bit extension signals on both primary and secondary interfaces
- Implements delayed transactions for all PCI configuration, I/O, and memory read commands, with up to three simultaneous transactions in each direction
- Provides 152-byte buffering (data and address) for upstream posted memory write commands and 88-byte buffering for downstream posted memory write commands, supporting up to 9 simultaneous upstream and 5 downstream posted write transactions
- Provides 152-byte upstream read data buffer and 152-byte downstream read data buffer
- Supports concurrent primary and secondary bus operation for traffic isolation
- Provides 10 secondary clock outputs:
- Low skew, allowing direct drive of optional slots
- Individual clock disable with automatic configuration capability during reset
- Provides arbitration support for 9 secondary bus devices:
- Programmable 2-level arbiter
- Hardware disable control for external arbiter support
- Provides a 4-pin general-purpose I/O interface accessible through device-specific configuration space
- Provides enhanced address decoding:
- 32-bit I/O address range
- 32-bit memory-mapped I/O address range
- 64-bit prefetchable memory address range
- ISA-aware mode for legacy device support within the first 64KB of the I/O address range
- VGA addressing and VGA palette snooping support
- Includes hot-plug support
- Supports PCI transaction forwarding for the following commands:
- All I/O and memory commands
- Type 1 to Type 1 configuration commands
- Type 1 to Type 0 configuration commands (downstream only)
- All Type 1 to special cycle configuration commands
- Includes downstream lock support
- Supports 5V and 3.3V signaling environments
- Available in 33MHz and 66MHz versions
- Provides IEEE Standard 1149.1 JTAG interface
Not available now
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Signal Buffers, Repeaters, Splitters | |
| Manufacturer | Intel/Altera | |
| Packaging | PBGA-304(31x31) | |
| Features | Address translation and window mapping;Error detection;Plug-and-play and power-on state management;Clock management;Protocol bridging |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Fully compliant with PCI Local Bus Specification Revision 2.1
- Fully compliant with PCI Power Management Specification Version 1.0
- Supports 64-bit extension signals on both primary and secondary interfaces
- Implements delayed transactions for all PCI configuration, I/O, and memory read commands, with up to three simultaneous transactions in each direction
- Provides 152-byte buffering (data and address) for upstream posted memory write commands and 88-byte buffering for downstream posted memory write commands, supporting up to 9 simultaneous upstream and 5 downstream posted write transactions
- Provides 152-byte upstream read data buffer and 152-byte downstream read data buffer
- Supports concurrent primary and secondary bus operation for traffic isolation
- Provides 10 secondary clock outputs:
- Low skew, allowing direct drive of optional slots
- Individual clock disable with automatic configuration capability during reset
- Provides arbitration support for 9 secondary bus devices:
- Programmable 2-level arbiter
- Hardware disable control for external arbiter support
- Provides a 4-pin general-purpose I/O interface accessible through device-specific configuration space
- Provides enhanced address decoding:
- 32-bit I/O address range
- 32-bit memory-mapped I/O address range
- 64-bit prefetchable memory address range
- ISA-aware mode for legacy device support within the first 64KB of the I/O address range
- VGA addressing and VGA palette snooping support
- Includes hot-plug support
- Supports PCI transaction forwarding for the following commands:
- All I/O and memory commands
- Type 1 to Type 1 configuration commands
- Type 1 to Type 0 configuration commands (downstream only)
- All Type 1 to special cycle configuration commands
- Includes downstream lock support
- Supports 5V and 3.3V signaling environments
- Available in 33MHz and 66MHz versions
- Provides IEEE Standard 1149.1 JTAG interface
Compliance & Export Codes
| Type | Details |
|---|---|
| ECCN | 4A994 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| ECCN | 4A994 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |