TI TMS320LF2402PGS

The TMS320LF240x devices, new members of the TMS320C24xTM generation of digital signal processor (DSP) controllers, are part of the TMS320C2000Tm platform of fixed-point DSPs. The 240x devices offer the enhanced TMS320Tm DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing C24xTM DSP controller devices, the 240x offers increased processing performance (30 MIPS) and a higher level of peripheral integration.

The 240x generation offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points required by various applications. Flash devices of up to 32K words offer a cost-effective reprogrammable solution for volume production. The 240x family also includes RoM devices that are fully pin-to-pin compatible with their Flash counterparts.

All 240x devices offer at least one event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion. Devices with dual event managers enable multiple motor and/or

• High-Performance Static CMoS Technology
• 33-ns Instruction Cycle Time (30 MHz)
• 30-MIPS Performance
• Low-Power 3.3-V Design
• Based on TMS320C2xx DSP CPU Core
• Code-Compatible With F243/F241/C242
• Instruction Set and Module Compatible With F240/C240
• Up to 32K Words x 16 Bits of Flash EEPROM (4 Sectors)
• Up to 2.5K Words x 16 Bits of Data/Program RAM
• 544 Words of Dual-Access RAM
• Up to 2K Words of Single-Access RAM
• SCl/SPI Bootloader
• Two Event-Manager (EV) Modules (EVA and EVB), Each Include:
  • Two 16-Bit General-Purpose Timers
  • Eight 16-Bit Pulse-Width Modulation (PWM) Channels Which Enable:
    • Three-Phase Inverter Control
    • Center- or Edge-Alignment of PWM Channels
    • Emergency PWM Channel Shutdown With External PDPINTx Pin
    • Programmable Deadband (Deadtime) Prevents Shoot-Through Faults
  • Three Capture Units For Time-Stamping of External Events
  • On-Chip Position Encoder Interface Circuitry
  • Synchronized Analog-to-Digital Conversion
  • Designed for AC Induction, BLDC, Switched Reluctance, and Stepper Motor Control
  • Applicable for Multiple Motor and/or Converter Control
• External Memory Interface (LF2407)
• 192K Words x 16 Bits of Total Memory: 64K Program, 64K Data, 64K I/O
• Watchdog (WD) Timer Module
• 10-Bit Analog-to-Digital Converter (ADC)
  • 8 or 16 Multiplexed Input Channels
  • 500 ns Minimum Conversion Time
  • Selectable Twin 8-Input Sequencers Triggered by Two Event Managers
• Controller Area Network (CAN) 2.0B Module
• Serial Communications Interface (SCl)
• 16-Bit Serial Peripheral Interface (SPI) Module
• Phase-Locked-Loop (PLL)-Based Clock Generation
• Up to 40 Individually Programmable, Multiplexed General-Purpose Input/ Output (GPIO) Pins
• Up to Five External Interrupts (Power Drive Protection, Reset, and Two Maskable Interrupts)
• Power Management:
  • Three Power-Down Modes
  • Ability to Power Down Each Peripheral Independently
• Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1
• Extended Temperature Options (A and S)
  • A: - 40℃ to 85℃
  • S: - 40℃ to 125℃

• Digital motor and motion control applications
• Digital motor control and power conversion applications
• Multiple motor and/or converter control