AMD/XILINX XCZU2CG-2SFVC784I

The Zynq UltraScale+ MPSoC family is based on the UltraScale MPSoC architecture. This family of products integrates a feature-rich 64-bit quad-core or dual-core Arm Cortex -A53 and dual-core Arm Cortex-R5F based processing system (PS) and Xilinx programmable logic (PL) UltraScale architecture in a single device. Also included are on-chip memory, multiport external memory interfaces, and a rich set of peripheral connectivity interfaces.

• Quad-core or dual-core
• CPU frequency: Up to 1.5GHz
• Extendable cache coherency Armv8-A Architecture
• 64-bit or 32-bit operating modes
• TrustZone security
• A64 instruction set in 64-bit mode, A32/T32 instruction set in 32-bit mode
• NEON Advanced SIMD media-processing engine
• Single/double precision Floating Point Unit (FPU)
• CoreSight and Embedded Trace Macrocell (ETM)
• Accelerator Coherency Port (ACP)
• AXI Coherency Extension (ACE)
• Power island gating for each processor core
• Arm Generic timers support
• Two system level triple-timer counters
• One watchdog timer
• One global system timer
• 32KB Level 1, 2-way set-associative instruction cache with parity (independent for each CPU)
• 32KB Level 1, 4-way set-associative data cache with ECC (independent for each CPU)
• 1MB 16-way set-associative Level 2 cache with ECC (shared between the CPUs)
• CPU frequency: Up to 600MHz
• Armv7-R Architecture
• A32/T32 instruction set
• Single/double precision Floating Point Unit (FPU)
• CoreSight and Embedded Trace Macrocell (ETM)
• Lock-step or independent operation
• One watchdog timer
• Two triple-timer counters
• 32KB Level 1, 4-way set-associative instruction and data cache with ECC (independent for each CPU)
• 128KB TCM with ECC (independent for each CPU) that can be combined to become 256KB in lockstep mode
• 256KB on-chip RAM (OCM) in PS with ECC
• Up to 36Mb on-chip RAM (UltraRAM) with ECC in PL
• Up to 35Mb on-chip RAM (block RAM) with ECC in PL
• Up to 11Mb on-chip RAM (distributed RAM) in PL
• Supports OpenGL ES 1.1 and 2.0
• Supports OpenVG 1.1
• GPU frequency: Up to 667MHz
• Single Geometry Processor, Two Pixel Processors
• Pixel Fill Rate: 2 Mpixels/sec/MHz
• Triangle Rate: 0.11 Mtriangles/sec/MHz
• 64KB L2 Cache
• Power island gating
• Multi-protocol dynamic memory controller
• 32-bit or 64-bit interfaces to DDR4, DDR3, DDR3L, or LPDDR3 memories, and 32-bit interface to LPDDR4 memory
• ECC support in 64-bit and 32-bit modes
• Up to 32GB of address space using single or dual rank of 8-, 16-, or 32-bit-wide memories
• eMMC4.51 Managed NAND flash support
• ONFI3.1 NAND flash with 24-bit ECC
• 1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or two Quad-SPI (8-bit) serial NOR flash
• Two DMA controllers of 8-channels each
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support
• Four dedicated PS-GTR receivers and transmitters supports up to 6.0Gb/s data rates
• Supports SGMII tri-speed Ethernet, PCI Express Gen2, Serial-ATA (SATA), USB3.0, and DisplayPort
• PCI Express — Compliant with PCIe 2.1 base specification
• Root complex and End Point configurations
• x1, x2, and x4 at Gen1 or Gen2 rates
• SATA Host
• 1.5, 3.0, and 6.0Gb/s data rates as defined by SATA Specification, revision 3.1
• Supports up to two channels
• DisplayPort Controller
• Up to 5.4Gb/s rate
• Up to two TX lanes (no RX support)
• Four 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support
• Scatter-gather DMA capability
• Recognition of IEEE Std 1588 rev.2 PTP frames
• GMII, RGMII, and SGMII interfaces
• Jumbo frames
• Two USB 3.0/2.0 Device, Host, or OTG peripherals, each supporting up to 12 endpoints
• USB 3.0/2.0 compliant device IP core
• Super-speed, high- speed, full-speed, and low-speed modes
• Intel XHCI- compliant USB host
• Two full CAN 2.0B-compliant CAN bus interfaces
• CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant
• Two SD/SDIO 2.0/eMMC4.51 compliant controllers
• Two full-duplex SPI ports with three peripheral chip selects
• Two high-speed UARTs (up to 1Mb/s)
• Two master and slave I2C interfaces
• Up to 78 flexible multiplexed I/O (MIO) (up to three banks of 26 1/Os) for peripheral pin assignment
• Up to 96 EMIOs (up to three banks of 32 1/Os) connected to the PL
• High-bandwidth connectivity within PS and between PS and PL
• Arm AMBA AXI4-based
• QoS support for latency and bandwidth control
• Cache Coherent Interconnect (CCI)
• System Memory Management Unit (SMMU)
• Xilinx Memory Protection Unit (XMPU)
• Power gates PS peripherals, power islands, and power domains
• Clock gates PS peripheral user firmware option
• Boots PS and configures PL
• Supports secure and non-secure boot modes
• On-chip voltage and temperature sensing
• Look-up tables (LUT)
• Flip-flops
• Cascadable adders
• True dual-port
• Up to 72 bits wide
• Configurable as dual 18Kb
• 288Kb dual-port
• 72 bits wide
• Error checking and correction
• 27×18 signed multiply
• 48-bit adder/accumulator
• 27-bit pre-adder
• Supports LVCMOS, LVDS, and SSTL 1.0V to 3.3V I/O
• Programmable I/O delay and SerD