These 36-bit UBTs combine D-type latches and D-type flip-flops, allowing data to flow in transparent, latch, and clocked modes. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, A data is latched if CLKAB remains at a HIGH or LOW logic level. If LEAB is LOW, A data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. B-to-A data flow is similar to A-to-B, but uses OEBA, LEBA, and CLKBA. Output enable OEAB is active HIGH. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in a high-impedance state. The output enables are complementary (OEAB is active HIGH, while OEBA is active LOW). When Vcc is between 0 and 2.1V, the device is in a high-impedance state during power-up or power-down. However, to ensure a high-impedance state above 2.1V, OE should be connected to Vcc through a pull-up resistor and to GND through a pull-down resistor; the minimum resistance value is determined by the sink/source current capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABTH32501 operates over a temperature range of -55°C to 125°C. The SN74ABTH32501 operates over a temperature range of -40°C to 85°C.
TI 5962-9557601NXD